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17 lines
293 B
Systemverilog
17 lines
293 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(r);
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output r;
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reg r;
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assign r = 1'b0; // Bad
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endmodule
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