Tests: Cover some previously uncovered warnings

src/V3GraphAcyc.cpp

@@ -345,7 +345,7 @@ void GraphAcyc::simplifyOut(GraphAcycVertex* avertexp) {
                 nextp = inEdgep->inNextp();
                 V3GraphVertex* inVertexp = inEdgep->fromp();
                 if (inVertexp == avertexp) {
-                    if (debug()) v3error("Non-cutable edge forms a loop, vertex=" << avertexp);
+                    if (debug()) v3error("Non-cutable vertex=" << avertexp);  // LCOV_EXCL_LINE
                     v3error("Circular logic when ordering code (non-cutable edge loop)");
                     m_origGraphp->reportLoops(
                         &V3GraphEdge::followNotCutable,

src/V3Unroll.cpp

@@ -438,7 +438,7 @@ private:
         if (m_generate) {  // Ignore for's when expanding genfor's
             iterateChildren(nodep);
         } else {
-            nodep->v3error("V3Begin should have removed standard FORs");
+            nodep->v3fatalSrc("V3Begin should have removed standard FORs");
         }
     }
 

test_regress/t/t_assoc_method_bad.out

@@ -50,4 +50,8 @@
                                    : ... In instance t
    27 |       a.shuffle;   
       |         ^~~~~~~
+%Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined'
+                                   : ... In instance t
+   29 |       a.bad_not_defined();
+      |         ^~~~~~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_assoc_method_bad.v

@@ -25,5 +25,7 @@ module t (/*AUTOARG*/);
       a.rsort;  // Not legal on assoc
       a.reverse;  // Not legal on assoc
       a.shuffle;  // Not legal on assoc
+
+      a.bad_not_defined();
    end
 endmodule

test_regress/t/t_assoc_wildcard_bad.out

@@ -70,4 +70,8 @@
                                      : ... In instance t
    43 |       a[x] = "bad";
       |        ^
+%Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined'
+                                     : ... In instance t
+   45 |       a.bad_not_defined();
+      |         ^~~~~~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_assoc_wildcard_bad.v

@@ -41,5 +41,7 @@ module t (/*AUTOARG*/);
       a.find_last_index;  // Not legal on wildcard
 
       a[x] = "bad";
+
+      a.bad_not_defined();
    end
 endmodule

test_regress/t/t_case_inside_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_case_inside_bad.v:9:7: Illegal to have inside on a casex/casez
+    9 |       casex (1'bx) inside
+      |       ^~~~~
+%Error: Exiting due to

test_regress/t/t_case_inside_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_case_inside_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   initial begin
+      casex (1'bx) inside
+        default: $stop;
+      endcase
+   end
+endmodule

test_regress/t/t_enum_bad_dup.out

@@ -0,0 +1,7 @@
+%Error: t/t_enum_bad_dup.v:10:19: Duplicate declaration of enum value: DUP_VALUE
+   10 |                   DUP_VALUE = 3
+      |                   ^~~~~~~~~
+        t/t_enum_bad_dup.v:9:19: ... Location of original declaration
+    9 |    typedef enum { DUP_VALUE = 2,
+      |                   ^~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_enum_bad_dup.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_enum_bad_dup.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   typedef enum { DUP_VALUE = 2,
+                  DUP_VALUE = 3
+                  } dup_t;
+
+endmodule

test_regress/t/t_enum_bad_wrap.out

@@ -0,0 +1,5 @@
+%Error: t/t_enum_bad_wrap.v:11:19: Enum value illegally wrapped around (IEEE 1800-2017 6.19)
+                                 : ... In instance t
+   11 |                   WRAPPED
+      |                   ^~~~~~~
+%Error: Exiting due to

test_regress/t/t_enum_bad_wrap.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_enum_bad_wrap.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   typedef enum [1:0] {
+                  PREWRAP = 2'd3,
+                  WRAPPED
+                  } wrap_t;
+
+endmodule

test_regress/t/t_enum_type_nomethod_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_enum_type_nomethod_bad.v:15:9: Unknown built-in enum method 'bad_no_such_method'
+                                         : ... In instance t
+   15 |       e.bad_no_such_method();
+      |         ^~~~~~~~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_enum_type_nomethod_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename}
+    );
+
+ok(1);
+1;

test_regress/t/t_enum_type_nomethod_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   typedef enum [3:0] {
+                       E01 = 1
+                       } my_t;
+
+   my_t e;
+
+   initial begin
+      e.bad_no_such_method();
+      $stop;
+   end
+
+endmodule

test_regress/t/t_flag_deprecated_bad.out

@@ -0,0 +1,7 @@
+%Warning-DEPRECATED: Option -O<letter> is deprecated. Use -f<optimization> or -fno-<optimization> instead.
+                     ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest
+                     ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message.
+%Warning-DEPRECATED: Option --prof-threads is deprecated. Use --prof-exec and --prof-pgo instead.
+%Warning-DEPRECATED: Option --trace-fst-thread is deprecated. Use --trace-fst with --trace-threads > 0.
+%Warning-DEPRECATED: Option order-clock-delay is deprecated and has no effect.
+%Error: Exiting due to

test_regress/t/t_flag_deprecated_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["-Ox --prof-threads --trace-fst-thread --order-clock-delay"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_flag_deprecated_bad.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+endmodule

test_regress/t/t_foreach_nindex_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_foreach_nindex_bad.v:12:34: foreach loop variables exceed number of indices of array
+   12 |       foreach (array[i, j, badk, badl]);   
+      |                                  ^~~~
+%Error: Exiting due to

test_regress/t/t_foreach_nindex_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_foreach_nindex_bad.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   int array[2][2];
+
+   initial begin
+      foreach (array[i, j, badk, badl]);  // bad
+
+      $stop;
+   end
+
+endmodule

test_regress/t/t_gen_nonconst_bad.out

@@ -0,0 +1,17 @@
+%Error: t/t_gen_nonconst_bad.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
+                                  : ... In instance t
+    8 |    if ($test$plusargs("BAD-non-constant")) begin
+      |        ^~~~~~~~~~~~~~
+%Error: t/t_gen_nonconst_bad.v:8:8: Generate If condition must evaluate to constant
+                                  : ... In instance t
+    8 |    if ($test$plusargs("BAD-non-constant")) begin
+      |        ^~~~~~~~~~~~~~
+%Error: t/t_gen_nonconst_bad.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
+                                   : ... In instance t
+   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
+      |       ^~~~~~~~~~~~~~
+%Error: t/t_gen_nonconst_bad.v:12:41: Generate Case item does not evaluate to constant
+                                    : ... In instance t
+   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
+      |                                         ^
+%Error: Exiting due to

test_regress/t/t_gen_nonconst_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_gen_nonconst_bad.v

@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   if ($test$plusargs("BAD-non-constant")) begin
+      initial $stop;
+   end
+   case (1)
+      $test$plusargs("BAD-non-constant"): initial $stop;
+   endcase
+
+endmodule

test_regress/t/t_inst_2star_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_inst_2star_bad.v:9:17: Duplicate .* in an instance
+    9 |    sub sub (.*, .*);
+      |                 ^~
+%Error: Exiting due to

test_regress/t/t_inst_2star_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_2star_bad.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   sub sub (.*, .*);
+
+endmodule
+
+module sub (input foo);
+endmodule

test_regress/t/t_lib_prot_delay_bad.out

@@ -0,0 +1,3 @@
+%Error-UNSUPPORTED: Unsupported: --lib-create with --timing and delays
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_lib_prot_delay_bad.pl

@@ -0,0 +1,26 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile (
+    verilator_flags2 => ["--protect-lib",
+                         "secret",
+                         "--protect-key",
+                         "secret-key",
+                         "--timing",
+                       ],
+    verilator_make_gcc => 0,
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_lib_prot_delay_bad.v

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
+
+module secret_impl;
+   initial begin
+      #10;
+      $stop;
+   end
+endmodule

test_regress/t/t_lint_contassreg_bad.out

@@ -0,0 +1,6 @@
+%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:11: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
+                                                  : ... In instance t
+   14 |    assign r = 1'b0;   
+      |           ^
+                   ... For error description see https://verilator.org/warn/CONTASSREG?v=latest
+%Error: Exiting due to

test_regress/t/t_lint_contassreg_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ['--language 1364-2001'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_lint_contassreg_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+
+module t(r);
+
+   output r;
+
+   reg r;
+
+   assign r = 1'b0;  // Bad
+
+endmodule

test_regress/t/t_lint_historical.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only"],
+    );
+
+ok(1);
+1;

test_regress/t/t_lint_historical.v

@@ -0,0 +1,92 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   // Test all warnings, including those that are historically removed still parse
+   // verilator lint_off ALWCOMBORDER
+   // verilator lint_off ASSIGNDLY
+   // verilator lint_off ASSIGNIN
+   // verilator lint_off BADSTDPRAGMA
+   // verilator lint_off BLKANDNBLK
+   // verilator lint_off BLKLOOPINIT
+   // verilator lint_off BLKSEQ
+   // verilator lint_off BSSPACE
+   // verilator lint_off CASEINCOMPLETE
+   // verilator lint_off CASEOVERLAP
+   // verilator lint_off CASEWITHX
+   // verilator lint_off CASEX
+   // verilator lint_off CASTCONST
+   // verilator lint_off CDCRSTLOGIC
+   // verilator lint_off CLKDATA
+   // verilator lint_off CMPCONST
+   // verilator lint_off COLONPLUS
+   // verilator lint_off COMBDLY
+   // verilator lint_off CONTASSREG
+   // verilator lint_off DEFPARAM
+   // verilator lint_off DECLFILENAME
+   // verilator lint_off DEPRECATED
+   // verilator lint_off RISEFALLDLY
+   // verilator lint_off MINTYPMAXDLY
+   // verilator lint_off ENDLABEL
+   // verilator lint_off EOFNEWLINE
+   // verilator lint_off GENCLK
+   // verilator lint_off HIERBLOCK
+   // verilator lint_off IFDEPTH
+   // verilator lint_off IGNOREDRETURN
+   // verilator lint_off IMPERFECTSCH
+   // verilator lint_off IMPLICIT
+   // verilator lint_off IMPORTSTAR
+   // verilator lint_off IMPURE
+   // verilator lint_off INCABSPATH
+   // verilator lint_off INFINITELOOP
+   // verilator lint_off INITIALDLY
+   // verilator lint_off INSECURE
+   // verilator lint_off LATCH
+   // verilator lint_off LITENDIAN
+   // verilator lint_off MODDUP
+   // verilator lint_off MULTIDRIVEN
+   // verilator lint_off MULTITOP
+   // verilator lint_off NOLATCH
+   // verilator lint_off NULLPORT
+   // verilator lint_off PINCONNECTEMPTY
+   // verilator lint_off PINMISSING
+   // verilator lint_off PINNOCONNECT
+   // verilator lint_off PINNOTFOUND
+   // verilator lint_off PKGNODECL
+   // verilator lint_off PROCASSWIRE
+   // verilator lint_off PROFOUTOFDATE
+   // verilator lint_off PROTECTED
+   // verilator lint_off RANDC
+   // verilator lint_off REALCVT
+   // verilator lint_off REDEFMACRO
+   // verilator lint_off SELRANGE
+   // verilator lint_off SHORTREAL
+   // verilator lint_off SPLITVAR
+   // verilator lint_off STMTDLY
+   // verilator lint_off SYMRSVDWORD
+   // verilator lint_off SYNCASYNCNET
+   // verilator lint_off TICKCOUNT
+   // verilator lint_off TIMESCALEMOD
+   // verilator lint_off UNDRIVEN
+   // verilator lint_off UNOPT
+   // verilator lint_off UNOPTFLAT
+   // verilator lint_off UNOPTTHREADS
+   // verilator lint_off UNPACKED
+   // verilator lint_off UNSIGNED
+   // verilator lint_off UNUSEDGENVAR
+   // verilator lint_off UNUSEDPARAM
+   // verilator lint_off UNUSEDSIGNAL
+   // verilator lint_off USERERROR
+   // verilator lint_off USERFATAL
+   // verilator lint_off USERINFO
+   // verilator lint_off USERWARN
+   // verilator lint_off VARHIDDEN
+   // verilator lint_off WAITCONST
+   // verilator lint_off WIDTH
+   // verilator lint_off WIDTHCONCAT
+   // verilator lint_off ZERODLY
+
+endmodule

test_regress/t/t_lint_pragma_protected_err.out

@@ -11,7 +11,31 @@
       |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 %Warning-PROTECTED: t/t_lint_pragma_protected_err.v:44:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
                     ... Use "/* verilator lint_off PROTECTED */" and lint_on around source to disable this message.
-%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:58:1: `pragma is missing a pragma_expression.
-   58 | `pragma
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:51:17: Illegal encoding type for `pragma protected encoding
+   51 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
+      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_lint_pragma_protected_err.v:51:17: Unsupported: only BASE64 is recognized for `pragma protected encoding
+   51 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
+      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+%Warning-PROTECTED: t/t_lint_pragma_protected_err.v:53:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:54:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+   54 | c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
+      | ^
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:55:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+   55 | IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
+      | ^
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:56:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+   56 | aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
+      | ^
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:57:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+   57 | ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
+      | ^
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:58:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+   58 | ZCBXb3JrIGFzIG==
+      | ^
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:59:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:59:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_err.v:67:1: `pragma is missing a pragma_expression.
+   67 | `pragma
       | ^~~~~~~
 %Error: Exiting due to

test_regress/t/t_lint_pragma_protected_err.v

@@ -48,6 +48,15 @@ aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
 ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
 ZCBXb3JrIGFzIG==
 
+`pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
+`pragma protect data_block
+aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy
+c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
+IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
+aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
+ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
+ZCBXb3JrIGFzIG==
+
 
 `pragma protect end_protected
 

test_regress/t/t_pp_defnettype_bad.out

@@ -0,0 +1,11 @@
+%Error-UNSUPPORTED: t/t_pp_defnettype_bad.v:7:1: Unsupported: `default_nettype of other than none or wire: '`default_nettype bad'
+    7 | `default_nettype bad_none_such
+      | ^~~~~~~~~~~~~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_pp_defnettype_bad.v:9:1: Unsupported: Verilog optional directive not implemented: '`default_trireg_strength this_is_optional'
+    9 | `default_trireg_strength this_is_optional
+      | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+%Error: t/t_pp_defnettype_bad.v:7:21: syntax error, unexpected IDENTIFIER
+    7 | `default_nettype bad_none_such
+      |                     ^~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_pp_defnettype_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_pp_defnettype_bad.v

@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`default_nettype bad_none_such
+
+`default_trireg_strength this_is_optional

test_regress/t/t_preproc_nodef_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_preproc_nodef_bad.v:7:1: Define or directive not defined: '`not_defined'
+    7 | `not_defined
+      | ^~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_preproc_nodef_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_nodef_bad.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`not_defined
+
+module t;
+endmodule

test_regress/t/t_string_type_methods_bad.out

@@ -10,4 +10,8 @@
                                           : ... In instance t
    17 |       s.itoa(1,2,3);   
       |         ^~~~
+%Error: t/t_string_type_methods_bad.v:18:9: Unknown built-in string method 'bad_no_such_method'
+                                          : ... In instance t
+   18 |       s.bad_no_such_method();   
+      |         ^~~~~~~~~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_string_type_methods_bad.v

@@ -15,6 +15,7 @@ module t (/*AUTOARG*/);
       i = s.len(0); // BAD
       s.itoa;  // BAD
       s.itoa(1,2,3);  // BAD
+      s.bad_no_such_method();  // BAD
    end
 
 endmodule

test_regress/t/t_unbounded_bad.out

@@ -0,0 +1,11 @@
+%Error-UNSUPPORTED: t/t_unbounded_bad.v:9:11: Unsupported/illegal unbounded ('$') in this context.
+                                            : ... In instance t
+    9 |       if ($) $stop;
+      |           ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Warning-WIDTH: t/t_unbounded_bad.v:9:7: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits.
+                                       : ... In instance t
+    9 |       if ($) $stop;
+      |       ^~
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_unbounded_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_unbounded_bad.v

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   initial begin
+      if ($) $stop;
+   end
+endmodule