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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
38 lines
595 B
Verilog
38 lines
595 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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integer top;
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initial begin
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begin : a
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integer lower;
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lower = 1;
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top = 1;
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if (lower != 1) $stop;
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begin : aa
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integer lev2;
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lev2 = 1;
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lower = 2;
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top = 2;
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end
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if (lower != 2) $stop;
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end
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begin : b
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integer lower;
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lower = 1;
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top = 2;
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begin : empty
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begin : empty
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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