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21 lines
372 B
Verilog
21 lines
372 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005-2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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value
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);
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input [3:0] value;
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always @ (/*AS*/value) begin
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case (value)
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4'b0000: $stop;
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4'b1xxx: $stop;
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default: $stop;
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endcase
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end
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endmodule
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