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39 lines
749 B
Systemverilog
39 lines
749 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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randc int i;
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function new;
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i = 0;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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bit ok = 0;
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Cls obj;
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initial begin
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int rand_result;
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int prev_i;
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for (int i = 0; i < 10; i++) begin
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obj = new;
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rand_result = obj.randomize();
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if (i > 0 && obj.i != prev_i) begin
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ok = 1;
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end
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prev_i = obj.i;
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end
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if (ok) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else $stop;
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end
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endmodule
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