Support 'randc' as alias to 'rand' (#2680)

* Add alias 'randc' to 'rand'

* Make the 'RANDC' warning; add tests

bin/verilator

@@ -4692,6 +4692,11 @@ declared before being used.
 Error that a procedural assignment is setting a wire. According to IEEE, a
 var/reg must be used as the target of procedural assignments.
 
+=item RANDC
+
+Warns that the 'randc' keyword is currently unsupported, and that it is
+being converted to 'rand'.
+
 =item REALCVT
 
 Warns that a real number is being implicitly rounded to an integer, with

src/V3Error.h

@@ -103,6 +103,7 @@ public:
         PINCONNECTEMPTY,// Cell pin connected by name with empty reference
         PKGNODECL,      // Error: Package/class needs to be predeclared
         PROCASSWIRE,    // Procedural assignment on wire
+        RANDC,          // Unsupported: 'randc' converted to 'rand'
         REALCVT,        // Real conversion
         REDEFMACRO,     // Redefining existing define macro
         SELRANGE,       // Selection index out of range
@@ -164,7 +165,7 @@ public:
             "LITENDIAN", "MODDUP",
             "MULTIDRIVEN", "MULTITOP",
             "PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY", "PKGNODECL", "PROCASSWIRE",
-            "REALCVT", "REDEFMACRO",
+            "RANDC", "REALCVT", "REDEFMACRO",
             "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
             "TICKCOUNT", "TIMESCALEMOD",
             "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS",

src/V3ParseImp.h

@@ -83,7 +83,10 @@ struct VMemberQualifiers {
     }
     void applyToNodes(AstVar* nodesp) const {
         for (AstVar* nodep = nodesp; nodep; nodep = VN_CAST(nodep->nextp(), Var)) {
-            // Ignored for now: m_randc
+            if (m_randc) {
+                nodep->v3warn(RANDC, "Unsupported: Converting 'randc' to 'rand'");
+                nodep->isRand(true);
+            }
             if (m_rand) nodep->isRand(true);
             if (m_local) nodep->isHideLocal(true);
             if (m_protected) nodep->isHideProtected(true);

test_regress/t/t_class_unsup_bad.pl

@@ -12,6 +12,7 @@ scenarios(vlt => 1);
 
 lint(
     fails => 1,
+    verilator_flags2 => ['-Wno-RANDC'],
     expect_filename => $Self->{golden_filename},
     );
 

test_regress/t/t_randc_ignore_unsup.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ['-Wno-RANDC'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_randc_ignore_unsup.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   randc int i;
+
+   function new;
+      i = 0;
+   endfunction
+
+endclass
+
+module t (/*AUTOARG*/);
+   bit ok = 0;
+
+   Cls obj;
+
+   initial begin
+      int rand_result;
+      int prev_i;
+      for (int i = 0; i < 10; i++) begin
+         obj = new;
+         rand_result = obj.randomize();
+         if (i > 0 && obj.i != prev_i) begin
+            ok = 1;
+         end
+         prev_i = obj.i;
+      end
+      if (ok) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else $stop;
+   end
+endmodule

test_regress/t/t_randc_unsup.out

@@ -0,0 +1,5 @@
+%Warning-RANDC: t/t_randc_unsup.v:8:14: Unsupported: Converting 'randc' to 'rand'
+    8 |    randc int i;
+      |              ^
+                ... Use "/* verilator lint_off RANDC */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_randc_unsup.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_randc_unsup.v

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   randc int i;
+endclass
+
+module t (/*AUTOARG*/);
+endmodule