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c0be8bcefb
verilator/test_regress/t/t_preproc.out
Wilson Snyder e0654dc218 Add --dump-defines.
2018-10-25 19:47:07 -04:00

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`line 1 "t/t_preproc.v" 1
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`line 1 "t/t_preproc_inc2.vh" 1
`line 2 "t/t_preproc_inc2.vh" 0
At file "t/t_preproc_inc2.vh" line 4
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`line 1 "t/t_preproc_inc3.vh" 1
`line 2 "inc3_a_filename_from_line_directive" 0
`line 6 "inc3_a_filename_from_line_directive" 0
At file "inc3_a_filename_from_line_directive" line 10
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`line 12 "t/t_preproc.v" 0
/*verilator pass_thru comment*/
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/*verilator pass_thru_comment2*/
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wire [3:0] q = {
1'b1 ,
1'b0 ,
1'b1 ,
1'b1
};
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text.
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foo bar
foobar2
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first part
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second part
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third part
{
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a,
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b,
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c}
Line_Preproc_Check 48
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deep deep
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"Inside: `nosubst"
"`nosubst"
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x y LLZZ x y
p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
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firstline comma","line LLZZ firstline comma","line
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x y LLZZ "x" y
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(a,b)(a,b)
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$display("left side: \"right side\"")
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bar_suffix more
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$c("Zap(\"",bug1,"\");");;
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$c("Zap(\"","bug2","\");");;
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initial begin
$display("pre thrupre thrumid thrupost post: \"right side\"");
$display("left side: \"right side\"");
$display("left side: \"right side\"");
$display("left_side: \"right_side\"");
$display("na: \"right_side\"");
$display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
$display("na: \"nana\"");
$display("left_side right_side: \"left_side right_side\"");
$display(": \"\"");
$display("left side: \"right side\"");
$display("left side: \"right side\"");
$display("standalone");
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$display("twoline: \"first second\"");
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
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module add1 ( input wire d1, output wire o1);
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wire tmp_d1 = d1;
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wire tmp_o1 = tmp_d1 + 1;
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assign o1 = tmp_o1 ;
endmodule
module add2 ( input wire d2, output wire o2);
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wire tmp_d2 = d2;
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wire tmp_o2 = tmp_d2 + 1;
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assign o2 = tmp_o2 ;
endmodule
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generate for (i=0; i<(3); i=i+1) begin
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psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";
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psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";
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end endgenerate
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module prot();
`protected
I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
#nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
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`endprotected
endmodule
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begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
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`line 1 "t/t_preproc_inc4.vh" 1
`line 2 "t/t_preproc_inc4.vh" 0
`line 5 "t/t_preproc_inc4.vh" 0
`line 7 "t/t_preproc_inc4.vh" 2
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$blah("ab,cd","e,f");
$blah(this.logfile,vec);
$blah(this.logfile,vec[1,2,3]);
$blah(this.logfile,{blah.name(), " is not foo"});
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`pragma foo = 1
`default_nettype none
`default_nettype uwire
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Line_Preproc_Check 213
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(p,q)
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(x,y)
Line_Preproc_Check 226
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beginend
beginend
"beginend"
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`\esc`def
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Not a \`define
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x,y)--bee submacro has comma paren
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$display("10 %d %d", $bits(foo), 10);
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assign a3 = ~b3 ;
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\
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def i
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1 /*verilator NOT IN DEFINE*/ (nodef)
2 /*verilator PART OF DEFINE*/ (hasdef)
3
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/*verilator NOT PART
OF DEFINE*/ (nodef)
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4
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/*verilator PART
OF DEFINE*/ (nodef)
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5 also in
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also3 (nodef)
HAS a NEW
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LINE
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EXP: clxx_scen
clxx_scen
EXP: clxx_scen
"clxx_scen"
EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
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do
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if (start("t/t_preproc.v", 340)) begin
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message({"Blah-", "clx_scen", " end"});
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end
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while(0);
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EXP: This is fooed
This is fooed
EXP: This is fooed_2
This is fooed_2
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np
np
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hello3hello3hello3
hello4hello4hello4hello4
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`line 1 "t/t_preproc_inc4.vh" 1
`line 2 "t/t_preproc_inc4.vh" 0
`line 5 "t/t_preproc_inc4.vh" 0
`line 7 "t/t_preproc_inc4.vh" 2
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Line_Preproc_Check 401
Line_Preproc_Check 407
"FOO \
BAR " "arg_line1 \
arg_line2" "FOO \
BAR "
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Line_Preproc_Check 410
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abc
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EXP: sonet_frame
sonet_frame
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EXP: sonet_frame
sonet_frame
EXP: sonet_frame
sonet_frame
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EXP: module zzz ; endmodule
module zzz ; endmodule
module zzz ; endmodule
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EXP: module a_b ; endmodule
module a_b ; endmodule
module a_b ; endmodule
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integer foo;
module t;
initial begin : \`LEX_CAT(a[0],_assignment)
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
initial begin : \a[0]_assignment_a[1]
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
initial begin : \`CAT(ff,bb)
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
initial begin : \`zzz
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
initial begin : \`FOO
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$write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
initial begin : \xx`FOO
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
initial $write("Slashed=`%s'\n", "1//2.3");
initial
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$display("%s%s","a1","b2c3\n");
endmodule
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$display("RAM0");
$display("CPU");
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XXE_FAMILY = XXE_
$display("XXE_ is defined");
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XYE_FAMILY = XYE_
$display("XYE_ is defined");
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XXS_FAMILY = XXS_some
$display("XXS_some is defined");
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XYS_FAMILY = XYS_foo
$display("XYS_foo is defined");
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(.mySig (myInterface.pa5),
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`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
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module pcc2_cfg;
generate
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covergroup a @(posedge b);
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c: coverpoint d iff ((c) === 1'b1); endgroup
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a u_a;
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initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
endgenerate
endmodule
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predef 0 0
predef 1 1
predef 2 2
predef 3 3
predef 10 10
predef 11 11
predef 20 20
predef 21 21
predef 22 22
predef 23 23
predef -2 -2
predef -1 -1
predef 0 0
predef 1 1
predef 2 2
`line 656 "t/t_preproc.v" 2
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