`line 1 "t/t_preproc.v" 1 `line 5 "t/t_preproc.v" 0 `line 7 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 4 `line 6 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 `line 6 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 10 `line 12 "inc3_a_filename_from_line_directive" 0 `line 15 "inc3_a_filename_from_line_directive" 0 `line 19 "inc3_a_filename_from_line_directive" 2 `line 6 "t/t_preproc_inc2.vh" 0 `line 8 "t/t_preproc_inc2.vh" 2 `line 7 "t/t_preproc.v" 0 `line 9 "t/t_preproc.v" 0 `line 12 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ `line 14 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ `line 16 "t/t_preproc.v" 0 `line 19 "t/t_preproc.v" 0 wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 29 "t/t_preproc.v" 0 text. `line 31 "t/t_preproc.v" 0 foo bar foobar2 `line 36 "t/t_preproc.v" 0 `line 40 "t/t_preproc.v" 0 `line 45 "t/t_preproc.v" 0 first part `line 46 "t/t_preproc.v" 0 second part `line 46 "t/t_preproc.v" 0 third part { `line 47 "t/t_preproc.v" 0 a, `line 47 "t/t_preproc.v" 0 b, `line 47 "t/t_preproc.v" 0 c} Line_Preproc_Check 48 `line 50 "t/t_preproc.v" 0 `line 52 "t/t_preproc.v" 0 `line 54 "t/t_preproc.v" 0 deep deep `line 58 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 63 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 69 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 71 "t/t_preproc.v" 0 x y LLZZ "x" y `line 74 "t/t_preproc.v" 0 (a,b)(a,b) `line 77 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 80 "t/t_preproc.v" 0 bar_suffix more `line 83 "t/t_preproc.v" 0 `line 85 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 86 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 88 "t/t_preproc.v" 0 `line 91 "t/t_preproc.v" 0 `line 94 "t/t_preproc.v" 0 initial begin $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side: \"left_side right_side\""); $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 115 "t/t_preproc.v" 0 $display("twoline: \"first second\""); $write("*-* All Finished *-*\n"); $finish; end endmodule `line 125 "t/t_preproc.v" 0 `line 128 "t/t_preproc.v" 0 `line 133 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 134 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 134 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 134 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); `line 137 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 137 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 137 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule `line 140 "t/t_preproc.v" 0 `line 146 "t/t_preproc.v" 0 `line 151 "t/t_preproc.v" 0 `line 151 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 151 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 151 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 151 "t/t_preproc.v" 0 end endgenerate `line 153 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 159 "t/t_preproc.v" 0 `endprotected endmodule `line 163 "t/t_preproc.v" 0 `line 173 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 177 "t/t_preproc.v" 0 `line 180 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 5 "t/t_preproc_inc4.vh" 0 `line 7 "t/t_preproc_inc4.vh" 2 `line 180 "t/t_preproc.v" 0 `line 181 "t/t_preproc.v" 0 `line 184 "t/t_preproc.v" 0 `line 186 "t/t_preproc.v" 0 `line 190 "t/t_preproc.v" 0 `line 193 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 199 "t/t_preproc.v" 0 `line 202 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 206 "t/t_preproc.v" 0 `line 209 "t/t_preproc.v" 0 `line 213 "t/t_preproc.v" 0 Line_Preproc_Check 213 `line 215 "t/t_preproc.v" 0 `line 218 "t/t_preproc.v" 0 (p,q) `line 225 "t/t_preproc.v" 0 (x,y) Line_Preproc_Check 226 `line 228 "t/t_preproc.v" 0 `line 231 "t/t_preproc.v" 0 beginend beginend "beginend" `line 239 "t/t_preproc.v" 0 `\esc`def `line 245 "t/t_preproc.v" 0 Not a \`define `line 247 "t/t_preproc.v" 0 x,y)--bee submacro has comma paren `line 255 "t/t_preproc.v" 0 $display("10 %d %d", $bits(foo), 10); `line 260 "t/t_preproc.v" 0 `line 265 "t/t_preproc.v" 0 `line 268 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 `line 282 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 282 "t/t_preproc.v" 0 `line 284 "t/t_preproc.v" 0 \ `line 293 "t/t_preproc.v" 0 `line 293 "t/t_preproc.v" 0 `line 293 "t/t_preproc.v" 0 def i `line 295 "t/t_preproc.v" 0 `line 297 "t/t_preproc.v" 0 `line 301 "t/t_preproc.v" 0 `line 307 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 309 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) `line 310 "t/t_preproc.v" 0 4 `line 310 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) `line 311 "t/t_preproc.v" 0 5 also in `line 311 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW `line 314 "t/t_preproc.v" 0 LINE `line 316 "t/t_preproc.v" 0 `line 318 "t/t_preproc.v" 0 `line 331 "t/t_preproc.v" 0 `line 334 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 340 "t/t_preproc.v" 0 do `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 340)) begin `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 340 "t/t_preproc.v" 0 end `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 while(0); `line 342 "t/t_preproc.v" 0 `line 344 "t/t_preproc.v" 0 `line 348 "t/t_preproc.v" 0 `line 348 "t/t_preproc.v" 0 `line 349 "t/t_preproc.v" 0 EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 356 "t/t_preproc.v" 0 np np `line 367 "t/t_preproc.v" 0 `line 370 "t/t_preproc.v" 0 `line 378 "t/t_preproc.v" 0 `line 382 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 `line 388 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 5 "t/t_preproc_inc4.vh" 0 `line 7 "t/t_preproc_inc4.vh" 2 `line 388 "t/t_preproc.v" 0 `line 389 "t/t_preproc.v" 0 `line 397 "t/t_preproc.v" 0 Line_Preproc_Check 401 Line_Preproc_Check 407 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 410 "t/t_preproc.v" 0 Line_Preproc_Check 410 `line 414 "t/t_preproc.v" 0 abc `line 424 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 430 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame EXP: sonet_frame sonet_frame `line 440 "t/t_preproc.v" 0 EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 447 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 452 "t/t_preproc.v" 0 integer foo; module t; initial begin : \`LEX_CAT(a[0],_assignment) `line 464 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end initial begin : \a[0]_assignment_a[1] `line 471 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end initial begin : \`CAT(ff,bb) `line 485 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end initial begin : \`zzz `line 491 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end initial begin : \`FOO `line 498 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO `line 500 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); initial $write("Slashed=`%s'\n", "1//2.3"); initial `line 531 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 534 "t/t_preproc.v" 0 `line 537 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 542 "t/t_preproc.v" 0 `line 547 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 554 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 561 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 568 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 575 "t/t_preproc.v" 0 `line 577 "t/t_preproc.v" 0 `line 585 "t/t_preproc.v" 0 `line 592 "t/t_preproc.v" 0 `line 599 "t/t_preproc.v" 0 `line 606 "t/t_preproc.v" 0 `line 608 "t/t_preproc.v" 0 `line 610 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), `line 614 "t/t_preproc.v" 0 `line 617 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 620 "t/t_preproc.v" 0 `line 628 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 630 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 630 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 630 "t/t_preproc.v" 0 a u_a; `line 630 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 634 "t/t_preproc.v" 0 predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 `line 656 "t/t_preproc.v" 2