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317 lines
11 KiB
C++
317 lines
11 KiB
C++
//*************************************************************************
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// DESCRIPTION: Verilator: Add temporaries, such as for inst nodes
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//
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// Code available from: http://www.veripool.org/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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// V3Inst's Transformations:
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//
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// Each module:
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// Pins:
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// Create a wire assign to interconnect to submodule
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <cstdio>
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#include <cstdarg>
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#include <unistd.h>
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#include <algorithm>
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#include "V3Global.h"
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#include "V3Inst.h"
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#include "V3Ast.h"
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#include "V3Changed.h"
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//######################################################################
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// Inst state, as a visitor of each AstNode
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class InstVisitor : public AstNVisitor {
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private:
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// NODE STATE
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// Cleared each Cell:
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// AstVar::user1p() -> AstNode*. Expression connected to given pin
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// AstVarRef::user1p() -> bool. True if created senitem for parent's connected signal
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// AstPin::user1p() -> bool. True if created assignment already
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AstUser1InUse m_inuser1;
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// STATE
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AstNodeModule* m_modp; // Current module
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AstCell* m_cellp; // Current cell
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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//int m_debug; int debug() { return m_debug; }
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// VISITORS
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virtual void visit(AstNodeModule* nodep, AstNUser*) {
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UINFO(4," MOD "<<nodep<<endl);
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//if (nodep->name() == "t_chg") m_debug = 9; else m_debug=0;
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m_modp = nodep;
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nodep->iterateChildren(*this);
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m_modp = NULL;
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}
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virtual void visit(AstCell* nodep, AstNUser*) {
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UINFO(4," CELL "<<nodep<<endl);
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m_cellp = nodep;
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//VV***** We reset user1p() on each cell!!!
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AstNode::user1ClearTree();
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// Collect pin expressions, so submod->varp->user1p() points to expression it connects to
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for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
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pinp->modVarp()->user1p(pinp->exprp());
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}
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nodep->iterateChildren(*this);
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m_cellp = NULL;
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}
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virtual void visit(AstPin* nodep, AstNUser*) {
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// PIN(p,expr) -> ASSIGNW(VARXREF(p),expr) (if sub's input)
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// or ASSIGNW(expr,VARXREF(p)) (if sub's output)
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UINFO(4," PIN "<<nodep<<endl);
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if (debug()>=9) nodep->dumpTree(cout," Pin_oldb: ");
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if (nodep->modVarp()->isOutOnly() && nodep->exprp()->castConst())
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nodep->v3error("Output port is connected to a constant pin, electrical short");
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// Use user1p on the PIN to indicate we created an assign for this pin
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if (!nodep->user1()) {
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nodep->user1(1);
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// Simplify it
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V3Inst::pinReconnectSimple(nodep, m_cellp, m_modp);
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// Make a ASSIGNW (expr, pin)
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AstNode* exprp = nodep->exprp()->cloneTree(false);
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if (nodep->width() != nodep->modVarp()->width())
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nodep->v3fatalSrc("Width mismatch, should have been handled in pinReconnectSimple\n");
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if (nodep->modVarp()->isInout()) {
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nodep->v3fatalSrc("Unsupported: Verilator is a 2-state simulator");
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} else if (nodep->modVarp()->isOutput()) {
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AstNode* rhsp = new AstVarXRef (exprp->fileline(), nodep->modVarp(), m_cellp->name(), false);
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rhsp->widthSignedFrom(nodep);
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AstAssignW* assp = new AstAssignW (exprp->fileline(), exprp, rhsp);
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m_modp->addStmtp(assp);
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} else if (nodep->modVarp()->isInput()) {
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// Don't bother moving constants now,
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// we'll be pushing the const down to the cell soon enough.
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AstNode* assp = new AstAssignW
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(exprp->fileline(),
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new AstVarXRef(exprp->fileline(), nodep->modVarp(), m_cellp->name(), true),
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exprp);
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m_modp->addStmtp(assp);
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if (debug()>=9) assp->dumpTree(cout," _new: ");
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} else {
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nodep->v3error("Assigned pin is neither input nor output");
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}
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}
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// We're done with the pin
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nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
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}
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virtual void visit(AstUdpTable* nodep, AstNUser*) {
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if (!v3Global.opt.bboxUnsup()) {
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nodep->v3error("Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables.");
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}
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}
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// Save some time
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virtual void visit(AstNodeAssign*, AstNUser*) {}
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virtual void visit(AstAlways*, AstNUser*) {}
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//--------------------
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// Default: Just iterate
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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public:
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// CONSTUCTORS
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InstVisitor(AstNode* nodep) {
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m_modp=NULL;
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m_cellp=NULL;
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//
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nodep->accept(*this);
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}
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virtual ~InstVisitor() {}
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};
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//######################################################################
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class InstDeVisitor : public AstNVisitor {
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// Find all cells with arrays, and convert to non-arrayed
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private:
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// STATE
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AstRange* m_cellRangep; // Range for arrayed instantiations, NULL for normal instantiations
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int m_instNum; // Current instantiation number
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int m_instLsb; // Current instantiation number
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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// VISITORS
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virtual void visit(AstCell* nodep, AstNUser*) {
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if (nodep->rangep()) {
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m_cellRangep = nodep->rangep();
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UINFO(4," CELL "<<nodep<<endl);
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// Make all of the required clones
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m_instLsb = m_cellRangep->lsbConst();
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for (m_instNum = m_instLsb; m_instNum<=m_cellRangep->msbConst(); m_instNum++) {
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AstCell* newp = nodep->cloneTree(false);
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nodep->addNextHere(newp);
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// Remove ranging and fix name
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newp->rangep()->unlinkFrBack()->deleteTree();
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// Somewhat illogically, we need to rename the orignal name of the cell too.
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// as that is the name users expect for dotting
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// The spec says we add [x], but that won't work in C...
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newp->name(newp->name()+"__BRA__"+cvtToStr(m_instNum)+"__KET__");
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newp->origName(newp->origName()+"__BRA__"+cvtToStr(m_instNum)+"__KET__");
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// Fixup pins
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newp->pinsp()->iterateAndNext(*this);
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if (debug()==9) { newp->dumpTree(cout,"newcell: "); cout<<endl; }
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}
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// Done. Delete original
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m_cellRangep=NULL;
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nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL;
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}
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}
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virtual void visit(AstPin* nodep, AstNUser*) {
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// Any non-direct pins need reconnection with a part-select
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if (m_cellRangep) {
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UINFO(4," PIN "<<nodep<<endl);
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int pinwidth = nodep->modVarp()->width();
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int expwidth = nodep->exprp()->width();
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if (expwidth == pinwidth) {
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// NOP: Arrayed instants: widths match so connect to each instance
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} else if (expwidth == pinwidth*m_cellRangep->width()) {
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// Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide)
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AstNode* exprp = nodep->exprp()->unlinkFrBack();
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bool inputPin = nodep->modVarp()->isInput();
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if (!inputPin && !exprp->castVarRef()) {
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nodep->v3error("Unsupported: Per-bit array instantiations with output connections to non-wires.");
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}
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exprp = new AstSel (exprp->fileline(), exprp,
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pinwidth*(m_instNum-m_instLsb),
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pinwidth);
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nodep->exprp(exprp);
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} else {
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nodep->v3fatalSrc("Width mismatch; V3Width should have errored out.");
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}
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}
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}
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// Save some time
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virtual void visit(AstNodeMath*, AstNUser*) {}
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//--------------------
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// Default: Just iterate
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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public:
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// CONSTUCTORS
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InstDeVisitor(AstNode* nodep) {
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m_cellRangep=NULL;
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m_instNum=0;
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m_instLsb=0;
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//
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nodep->accept(*this);
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}
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virtual ~InstDeVisitor() {}
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};
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//######################################################################
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// Inst class functions
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void V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* modp) {
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// If a pin connection is "simple" leave it as-is
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// Else create a intermediate wire to perform the interconnect
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// Note this module calles cloneTree() via new AstVar
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AstVar* pinVarp = pinp->modVarp();
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AstVarRef* connectRefp = pinp->exprp()->castVarRef();
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AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
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AstBasicDType* connBasicp = NULL;
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
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//
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if (connectRefp
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&& connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
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&& !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
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// Done. Same data type
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} else if (connBasicp
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&& pinBasicp
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&& connBasicp->width() == pinBasicp->width()
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&& connBasicp->lsb() == pinBasicp->lsb()
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&& !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
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&& pinp->width() == pinVarp->width()
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&& 1) {
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// Done. One to one interconnect won't need a temporary variable.
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} else if (pinp->exprp()->castConst()) {
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// Done. Constant.
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} else {
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// Make a new temp wire
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//if (1||debug()>=9) { pinp->dumpTree(cout,"in_pin:"); }
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AstAssignW* assignp = NULL;
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AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
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string newvarname = "__Vcellinp__"+cellp->name()+"__"+pinp->name();
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AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
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modp->addStmtp(newvarp);
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if (pinVarp->isInout()) {
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pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be direct one-to-one connection (without any expression)");
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} else if (pinVarp->isOutput()) {
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// See also V3Inst
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AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
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if (pinp->width() > rhsp->width()) {
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if (rhsp->isSigned()) {
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rhsp = new AstExtendS(pinp->fileline(), rhsp);
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} else {
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rhsp = new AstExtend (pinp->fileline(), rhsp);
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}
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} else if (pinp->width() < rhsp->width()) {
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rhsp = new AstSel (pinp->fileline(), rhsp, 0, pinp->widthMin());
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}
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rhsp->widthSignedFrom(pinp);
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assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, true));
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} else {
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// V3 width should have range/extended to make the widths correct
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if (pinexprp->width() != pinVarp->width()) pinp->v3fatalSrc("Input pin width mismatch");
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assignp = new AstAssignW (pinp->fileline(),
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new AstVarRef(pinp->fileline(), newvarp, true),
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pinexprp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
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}
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pinp->widthSignedFrom(pinp->exprp());
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if (assignp) modp->addStmtp(assignp);
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//if (1||debug()) { pinp->dumpTree(cout," out:"); }
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//if (1||debug()) { assignp->dumpTree(cout," aout:"); }
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}
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}
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//######################################################################
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// Inst class visitor
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void V3Inst::instAll(AstNetlist* nodep) {
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UINFO(2,__FUNCTION__<<": "<<endl);
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InstVisitor visitor (nodep);
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}
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void V3Inst::dearrayAll(AstNetlist* nodep) {
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UINFO(2,__FUNCTION__<<": "<<endl);
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InstDeVisitor visitor (nodep);
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}
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