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Clock domain crossing checks
This commit is contained in:
Wilson Snyder
parent
a03a540156
commit
bf860b21d7
2
Changes
2
Changes
@ -26,6 +26,8 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Add VARHIDDEN warning when signal name hides module name.
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*** Add experimental clock domain crossing checks.
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**** Support optional cell parenthesis, bug179. [by Byron Bradley]
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**** Support for loop i++, ++i, i--, --i, bug175. [by Byron Bradley]
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@ -193,6 +193,7 @@ descriptions in the next sections for more information.
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--bbox-unsup Blackbox unsupported language features
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--bin <filename> Override Verilator binary
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--cc Create C++ output
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--cdc Clock domain crossing analysis
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--compiler <compiler-name> Tune for specified C++ compiler
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--coverage Enable all coverage
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--coverage-line Enable line coverage
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@ -254,6 +255,7 @@ descriptions in the next sections for more information.
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+define+<var>+<value> Set preprocessor define
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+incdir+<dir> Directory to search for includes
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+libext+<ext>+[ext]... Extensions for finding modules
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+notimingchecks Ignored
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=head1 ARGUMENTS
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@ -308,6 +310,17 @@ output files.
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Specifies C++ without SystemC output mode; see also --sc and --sp.
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=item --cdc
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Experimental. Perform some clock domain crossing checks and issue related
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warnings. Additional warning information is written to the file
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{prefix}__cdc.txt. Generally used with --lint-only.
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Currently only checks that asynchronous flop reset terms come from primary
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inputs (a check that most other CDC tools missed, so it was put here). If
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you have interest in adding more traditional CDC checks, please contact the
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authors.
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=item --compiler I<compiler-name>
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Enables tunings and work-arounds for the specified C++ compiler.
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@ -992,6 +1005,7 @@ In certain optimization modes, it also creates:
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{prefix}__Syms.cpp // Global symbol table C++
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{prefix}__Syms.h // Global symbol table header
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{prefix}__Trace.cpp // Wave file generation code (--trace)
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{prefix}__cdc.txt // Clock Domain Crossing checks (--cdc)
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{prefix}__stats.txt // Statistics (--stats)
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It also creates internal files that can be mostly ignored:
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@ -155,6 +155,7 @@ RAW_OBJS = \
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V3Broken.o \
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V3Case.o \
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V3Cast.o \
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V3Cdc.o \
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V3Changed.o \
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V3Clean.o \
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V3ClkGater.o \
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629
src/V3Cdc.cpp
Normal file
629
src/V3Cdc.cpp
Normal file
@ -0,0 +1,629 @@
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//*************************************************************************
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// DESCRIPTION: Verilator: Clock Domain Crossing Lint
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//
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// Code available from: http://www.veripool.org/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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// V3Cdc's Transformations:
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//
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// Create V3Graph-ish graph
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// Find all negedge reset flops
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// Trace back to previous flop
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <cstdio>
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#include <cstdarg>
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#include <unistd.h>
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#include <algorithm>
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#include <iomanip>
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#include <vector>
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#include <deque>
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#include <list>
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#include <memory>
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#include "V3Global.h"
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#include "V3Cdc.h"
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#include "V3Ast.h"
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#include "V3Graph.h"
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#include "V3Const.h"
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#include "V3EmitV.h"
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#include "V3File.h"
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//######################################################################
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class CdcBaseVisitor : public AstNVisitor {
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public:
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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};
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//######################################################################
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// Support classes
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class CdcEitherVertex : public V3GraphVertex {
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AstScope* m_scopep;
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AstNode* m_nodep;
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AstSenTree* m_srcDomainp;
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bool m_srcDomainSet;
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AstSenTree* m_dstDomainp;
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bool m_dstDomainSet;
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bool m_asyncPath;
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public:
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CdcEitherVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep)
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: V3GraphVertex(graphp), m_scopep(scopep), m_nodep(nodep)
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, m_srcDomainp(NULL), m_srcDomainSet(false)
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, m_dstDomainp(NULL), m_dstDomainSet(false)
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, m_asyncPath(false) {}
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virtual ~CdcEitherVertex() {}
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// Accessors
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AstScope* scopep() const { return m_scopep; }
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AstNode* nodep() const { return m_nodep; }
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AstSenTree* srcDomainp() const { return m_srcDomainp; }
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void srcDomainp(AstSenTree* nodep) { m_srcDomainp = nodep; }
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bool srcDomainSet() const { return m_srcDomainSet; }
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void srcDomainSet(bool flag) { m_srcDomainSet = flag; }
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AstSenTree* dstDomainp() const { return m_dstDomainp; }
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void dstDomainp(AstSenTree* nodep) { m_dstDomainp = nodep; }
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bool dstDomainSet() const { return m_dstDomainSet; }
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void dstDomainSet(bool flag) { m_dstDomainSet = flag; }
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bool asyncPath() const { return m_asyncPath; }
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void asyncPath(bool flag) { m_asyncPath = flag; }
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};
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class CdcVarVertex : public CdcEitherVertex {
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AstVarScope* m_varScp;
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int m_cntAsyncRst;
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bool m_fromFlop;
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public:
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CdcVarVertex(V3Graph* graphp, AstScope* scopep, AstVarScope* varScp)
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: CdcEitherVertex(graphp, scopep, varScp), m_varScp(varScp), m_cntAsyncRst(0), m_fromFlop(false) {}
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virtual ~CdcVarVertex() {}
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// Accessors
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AstVarScope* varScp() const { return m_varScp; }
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virtual string name() const { return (cvtToStr((void*)m_varScp)+" "+varScp()->name()); }
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virtual string dotColor() const { return fromFlop() ? "green" : cntAsyncRst() ? "red" : "blue"; }
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int cntAsyncRst() const { return m_cntAsyncRst; }
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void cntAsyncRst(int flag) { m_cntAsyncRst=flag; }
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bool fromFlop() const { return m_fromFlop; }
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void fromFlop(bool flag) { m_fromFlop = flag; }
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};
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class CdcLogicVertex : public CdcEitherVertex {
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bool m_safe;
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public:
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CdcLogicVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep, AstSenTree* sensenodep)
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: CdcEitherVertex(graphp,scopep,nodep), m_safe(true) { srcDomainp(sensenodep); dstDomainp(sensenodep); }
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virtual ~CdcLogicVertex() {}
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// Accessors
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virtual string name() const { return (cvtToStr((void*)nodep())+"@"+scopep()->prettyName()); }
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virtual string dotColor() const { return safe() ? "black" : "yellow"; }
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bool safe() const { return m_safe; }
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void clearSafe(AstNode* nodep) { m_safe = false; nodep->user3(true); }
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};
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//######################################################################
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// Cdc class functions
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class CdcVisitor : public CdcBaseVisitor {
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private:
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// NODE STATE
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//Entire netlist:
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// AstVarScope::user1p -> CdcVarVertex* for usage var, 0=not set yet
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// {statement}Node::user1p -> CdcLogicVertex* for this statement
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// AstNode::user3 -> bool True indicates to print %% (via V3EmitV)
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AstUser1InUse m_inuser1;
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AstUser3InUse m_inuser3;
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// STATE
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V3Graph m_graph; // Scoreboard of var usages/dependencies
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CdcLogicVertex* m_logicVertexp; // Current statement being tracked, NULL=ignored
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AstScope* m_scopep; // Current scope being processed
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AstNodeModule* m_modp; // Current module
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AstSenTree* m_domainp; // Current sentree
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bool m_inDly; // In delayed assign
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int m_senNumber; // Number of senitems
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string m_ofFilename; // Output filename
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ofstream* m_ofp; // Output file
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// METHODS
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void iterateNewStmt(AstNode* nodep) {
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if (m_scopep) {
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UINFO(4," STMT "<<nodep<<endl);
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m_logicVertexp = new CdcLogicVertex(&m_graph, m_scopep, nodep, m_domainp);
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if (m_domainp && m_domainp->hasClocked()) { // To/from a flop
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m_logicVertexp->srcDomainp(m_domainp);
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m_logicVertexp->srcDomainSet(true);
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m_logicVertexp->dstDomainp(m_domainp);
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m_logicVertexp->dstDomainSet(true);
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}
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m_senNumber = 0;
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nodep->iterateChildren(*this);
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m_logicVertexp = NULL;
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if (0 && debug()>=9) {
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UINFO(9, "Trace Logic:\n");
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nodep->dumpTree(cout, "-log1: ");
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}
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}
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}
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CdcVarVertex* makeVarVertex(AstVarScope* varscp) {
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CdcVarVertex* vertexp = (CdcVarVertex*)(varscp->user1p());
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if (!vertexp) {
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UINFO(6,"New vertex "<<varscp<<endl);
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vertexp = new CdcVarVertex(&m_graph, m_scopep, varscp);
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varscp->user1p(vertexp);
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if (varscp->varp()->isIO() && varscp->scopep()->isTop()) {}
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if (varscp->varp()->isUsedClock()) {}
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}
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if (m_senNumber > 1) vertexp->cntAsyncRst(vertexp->cntAsyncRst()+1);
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return vertexp;
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}
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string pad(unsigned column, const string& in) {
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string out = in;
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while (out.length()<column) out += ' ';
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return out;
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}
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void analyze();
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void analyzeReset();
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void edgeReport() {
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// Make report of all signal names and what clock edges they have
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UINFO(3,__FUNCTION__<<": "<<endl);
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// Trace all sources and sinks
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for (int traceDests=0; traceDests<2; ++traceDests) {
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UINFO(9, " Trace Direction "<<(traceDests?"dst":"src")<<endl);
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m_graph.userClearVertices(); // user1: bool - was analyzed
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for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
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if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(itp)) {
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UINFO(9, " Trace One edge: "<<vvertexp<<endl);
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edgeDomainRecurse(vvertexp, traceDests, 0);
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}
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}
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}
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string filename = v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__cdc_edges.txt";
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const auto_ptr<ofstream> ofp (V3File::new_ofstream(filename));
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if (ofp->fail()) v3fatalSrc("Can't write "<<filename);
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*ofp<<"Edge Report for "<<v3Global.opt.prefix()<<endl;
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deque<string> report; // Sort output by name
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for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
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if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(itp)) {
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AstVar* varp = vvertexp->varScp()->varp();
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if (1) { // varp->isPrimaryIO()
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const char* whatp = "wire";
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if (varp->isPrimaryIO()) whatp = (varp->isInout()?"inout":varp->isInput()?"input":"output");
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ostringstream os;
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os.setf(ios::left);
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os<<" "<<setw(8)<<whatp;
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os<<" "<<setw(40)<<vvertexp->varScp()->prettyName();
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os<<" SRC=";
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if (vvertexp->srcDomainp()) V3EmitV::verilogForTree(vvertexp->srcDomainp(), os);
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os<<" DST=";
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if (vvertexp->dstDomainp()) V3EmitV::verilogForTree(vvertexp->dstDomainp(), os);
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os<<"\n";
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report.push_back(os.str());
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}
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}
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}
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sort(report.begin(), report.end());
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for (deque<string>::iterator it = report.begin(); it!=report.end(); ++it) {
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*ofp << *it;
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}
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}
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string spaces(int level) { string out; while (level--) out+=" "; return out; }
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void edgeDomainRecurse(CdcEitherVertex* vertexp, bool traceDests, int level) {
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// Scan back to inputs/outputs, flops, and compute clock domain information
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UINFO(8,spaces(level)<<" Tracein "<<vertexp<<endl);
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if (vertexp->user()) return; // Mid-Processed - prevent loop
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vertexp->user(true);
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// Variables from flops already are domained
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if (traceDests ? vertexp->dstDomainSet() : vertexp->srcDomainSet()) return; // Fully computed
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typedef set<AstSenTree*> SenSet;
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SenSet senouts; // List of all sensitivities for new signal
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if (CdcLogicVertex* vvertexp = dynamic_cast<CdcLogicVertex*>(vertexp)) {
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if (vvertexp) {} // Unused
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}
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else if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(vertexp)) {
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// If primary I/O, give it domain of the input
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AstVar* varp = vvertexp->varScp()->varp();
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if (varp->isPrimaryIO() && varp->isInput() && !traceDests) {
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senouts.insert(new AstSenTree(varp->fileline(), new AstSenItem(varp->fileline(), AstSenItem::Combo())));
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}
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}
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// Now combine domains of sources/dests
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if (traceDests) {
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for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {
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CdcEitherVertex* eToVertexp = (CdcEitherVertex*)edgep->top();
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edgeDomainRecurse(eToVertexp, traceDests, level+1);
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if (eToVertexp->dstDomainp()) senouts.insert(eToVertexp->dstDomainp());
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}
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} else {
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for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
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CdcEitherVertex* eFromVertexp = (CdcEitherVertex*)edgep->fromp();
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edgeDomainRecurse(eFromVertexp, traceDests, level+1);
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if (eFromVertexp->srcDomainp()) senouts.insert(eFromVertexp->srcDomainp());
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}
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}
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// Convert list of senses into one sense node
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AstSenTree* senoutp = NULL;
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bool senedited = false;
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for (SenSet::iterator it=senouts.begin(); it!=senouts.end(); ++it) {
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if (!senoutp) senoutp = *it;
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else {
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if (!senedited) {
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senedited = true;
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senoutp = senoutp->cloneTree(true);
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}
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senoutp->addSensesp((*it)->sensesp()->cloneTree(true));
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}
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}
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// If multiple domains need to do complicated optimizations
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if (senedited) {
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senoutp = V3Const::constifyExpensiveEdit(senoutp)->castSenTree();
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}
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if (traceDests) {
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vertexp->dstDomainSet(true); // Note it's set - domainp may be null, so can't use that
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vertexp->dstDomainp(senoutp);
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if (debug()>=9) {
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UINFO(9,spaces(level)+" Tracedst "<<vertexp);
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if (senoutp) V3EmitV::verilogForTree(senoutp, cout); cout<<endl;
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}
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} else {
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vertexp->srcDomainSet(true); // Note it's set - domainp may be null, so can't use that
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vertexp->srcDomainp(senoutp);
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if (debug()>=9) {
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UINFO(9,spaces(level)+" Tracesrc "<<vertexp);
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if (senoutp) V3EmitV::verilogForTree(senoutp, cout); cout<<endl;
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}
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}
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}
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CdcEitherVertex* traceAsyncRecurse(CdcEitherVertex* vertexp, uint32_t did_value, bool mark);
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void dumpAsync(CdcVarVertex* vertexp, CdcEitherVertex* markp);
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void dumpAsyncRecurse(CdcEitherVertex* vertexp, const string& prefix, const string& blank);
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void warnAndFile(AstNode* nodep, V3ErrorCode code, const string& msg) {
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static bool told_file = false;
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nodep->v3warnCode(code,msg);
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if (!told_file) {
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told_file = 1;
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cerr<<V3Error::msgPrefix()<<" See details in "<<m_ofFilename<<endl;
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}
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*m_ofp<<"%Warning-"<<code.ascii()<<": "<<nodep->fileline()<<" "<<msg<<endl;
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}
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void clearNodeSafe(AstNode* nodep) {
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// Need to not clear if warnings are off (rather than when report it)
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// as bypassing this warning may turn up another path that isn't warning off'ed.
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if (m_logicVertexp && !nodep->fileline()->warnIsOff(V3ErrorCode::CDCRSTLOGIC)) {
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UINFO(9,"Clear safe "<<nodep<<endl);
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m_logicVertexp->clearSafe(nodep);
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}
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}
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// VISITORS
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virtual void visit(AstNodeModule* nodep, AstNUser*) {
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m_modp = nodep;
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nodep->iterateChildren(*this);
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m_modp = NULL;
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}
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virtual void visit(AstScope* nodep, AstNUser*) {
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UINFO(4," SCOPE "<<nodep<<endl);
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m_scopep = nodep;
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m_logicVertexp = NULL;
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nodep->iterateChildren(*this);
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m_scopep = NULL;
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}
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virtual void visit(AstActive* nodep, AstNUser*) {
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// Create required blocks and add to module
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UINFO(4," BLOCK "<<nodep<<endl);
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m_domainp = nodep->sensesp();
|
||||
if (!m_domainp || m_domainp->hasCombo() || m_domainp->hasClocked()) { // IE not hasSettle/hasInitial
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
m_domainp = NULL;
|
||||
}
|
||||
virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
|
||||
if (m_scopep) {
|
||||
if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block\n");
|
||||
AstVarScope* varscp = nodep->varScopep();
|
||||
if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
|
||||
CdcVarVertex* varvertexp = makeVarVertex(varscp);
|
||||
UINFO(5," VARREF to "<<varscp<<endl);
|
||||
// We use weight of one; if we ref the var more than once, when we simplify,
|
||||
// the weight will increase
|
||||
if (nodep->lvalue()) {
|
||||
new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1);
|
||||
if (m_inDly) {
|
||||
varvertexp->fromFlop(true);
|
||||
varvertexp->srcDomainp(m_domainp);
|
||||
varvertexp->srcDomainSet(true);
|
||||
}
|
||||
} else {
|
||||
new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
virtual void visit(AstAssignDly* nodep, AstNUser*) {
|
||||
m_inDly = true;
|
||||
nodep->iterateChildren(*this);
|
||||
m_inDly = false;
|
||||
}
|
||||
virtual void visit(AstSenItem* nodep, AstNUser*) {
|
||||
// Note we look at only AstSenItems, not AstSenGate's
|
||||
// The gating term of a AstSenGate is normal logic
|
||||
m_senNumber++;
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstAlways* nodep, AstNUser*) {
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
virtual void visit(AstCFunc* nodep, AstNUser*) {
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
virtual void visit(AstSenGate* nodep, AstNUser*) {
|
||||
// First handle the clock part will be handled in a minute by visit AstSenItem
|
||||
// The logic gating term is delt with as logic
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
virtual void visit(AstAssignAlias* nodep, AstNUser*) {
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
virtual void visit(AstAssignW* nodep, AstNUser*) {
|
||||
iterateNewStmt(nodep);
|
||||
}
|
||||
|
||||
// Math that shouldn't cause us to clear safe
|
||||
virtual void visit(AstConst* nodep, AstNUser*) { }
|
||||
virtual void visit(AstReplicate* nodep, AstNUser*) {
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstConcat* nodep, AstNUser*) {
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstNot* nodep, AstNUser*) {
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstSel* nodep, AstNUser*) {
|
||||
if (!nodep->lsbp()->castConst()) clearNodeSafe(nodep);
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstNodeSel* nodep, AstNUser*) {
|
||||
if (!nodep->bitp()->castConst()) clearNodeSafe(nodep);
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
|
||||
// Ignores
|
||||
virtual void visit(AstInitial* nodep, AstNUser*) { }
|
||||
virtual void visit(AstTraceInc* nodep, AstNUser*) { }
|
||||
virtual void visit(AstCoverToggle* nodep, AstNUser*) { }
|
||||
|
||||
//--------------------
|
||||
// Default
|
||||
virtual void visit(AstNodeMath* nodep, AstNUser*) {
|
||||
clearNodeSafe(nodep);
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
virtual void visit(AstNode* nodep, AstNUser*) {
|
||||
nodep->iterateChildren(*this);
|
||||
}
|
||||
|
||||
public:
|
||||
// CONSTUCTORS
|
||||
CdcVisitor(AstNode* nodep) {
|
||||
m_logicVertexp = NULL;
|
||||
m_scopep = NULL;
|
||||
m_modp = NULL;
|
||||
m_domainp = NULL;
|
||||
m_inDly = false;
|
||||
m_senNumber = 0;
|
||||
|
||||
// Make report of all signal names and what clock edges they have
|
||||
string filename = v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__cdc.txt";
|
||||
m_ofp = V3File::new_ofstream(filename);
|
||||
if (m_ofp->fail()) v3fatalSrc("Can't write "<<filename);
|
||||
m_ofFilename = filename;
|
||||
*m_ofp<<"CDC Report for "<<v3Global.opt.prefix()<<endl;
|
||||
*m_ofp<<"Each dump below traces a variable from a flop back through logic.\n";
|
||||
*m_ofp<<"First the variable is listed, then the logic that creates it, then all variables\n";
|
||||
*m_ofp<<"feeding that logic, recursively backwards to the sourcing flop(s).\n";
|
||||
*m_ofp<<"%% Indicates nodes considered potentially unsafe.\n";
|
||||
|
||||
nodep->accept(*this);
|
||||
analyze();
|
||||
//edgeReport(); // Not useful at the moment
|
||||
|
||||
if (0) { *m_ofp<<"\nDBG-test-dumper\n"; V3EmitV::verilogPrefixedTree(nodep, *m_ofp, "DBG ",true); *m_ofp<<endl; }
|
||||
}
|
||||
virtual ~CdcVisitor() {
|
||||
if (m_ofp) { delete m_ofp; m_ofp = NULL; }
|
||||
}
|
||||
};
|
||||
|
||||
//######################################################################
|
||||
// Cdc class functions
|
||||
|
||||
class CdcDumpVisitor : public CdcBaseVisitor {
|
||||
private:
|
||||
// NODE STATE
|
||||
//Entire netlist:
|
||||
// {statement}Node::user3p -> bool, indicating not safe
|
||||
ofstream* m_ofp; // Output file
|
||||
string m_prefix;
|
||||
|
||||
virtual void visit(AstNode* nodep, AstNUser*) {
|
||||
*m_ofp<<m_prefix;
|
||||
if (nodep->user3()) *m_ofp<<" %%";
|
||||
else *m_ofp<<" ";
|
||||
*m_ofp<<nodep->prettyTypeName()<<" "<<endl;
|
||||
string lastPrefix = m_prefix;
|
||||
m_prefix = lastPrefix + "1:";
|
||||
nodep->op1p()->iterateAndNext(*this);
|
||||
m_prefix = lastPrefix + "2:";
|
||||
nodep->op2p()->iterateAndNext(*this);
|
||||
m_prefix = lastPrefix + "3:";
|
||||
nodep->op3p()->iterateAndNext(*this);
|
||||
m_prefix = lastPrefix + "4:";
|
||||
nodep->op4p()->iterateAndNext(*this);
|
||||
m_prefix = lastPrefix;
|
||||
}
|
||||
|
||||
public:
|
||||
// CONSTUCTORS
|
||||
CdcDumpVisitor(AstNode* nodep, ofstream* ofp, const string& prefix) {
|
||||
m_ofp = ofp;
|
||||
m_prefix = prefix;
|
||||
nodep->accept(*this);
|
||||
}
|
||||
virtual ~CdcDumpVisitor() {}
|
||||
};
|
||||
|
||||
//######################################################################
|
||||
|
||||
void CdcVisitor::analyze() {
|
||||
UINFO(3,__FUNCTION__<<": "<<endl);
|
||||
//if (debug()>6) m_graph.dump();
|
||||
if (debug()>6) m_graph.dumpDotFilePrefixed("cdc_pre");
|
||||
m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue);
|
||||
m_graph.dumpDotFilePrefixed("cdc_simp");
|
||||
//
|
||||
analyzeReset();
|
||||
}
|
||||
|
||||
void CdcVisitor::analyzeReset() {
|
||||
// Find all async reset wires, and trace backwards
|
||||
for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
|
||||
if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(itp)) {
|
||||
if (vvertexp->cntAsyncRst()) {
|
||||
m_graph.userClearVertices(); // user1: bool - was analyzed
|
||||
UINFO(9, " Trace One async: "<<vvertexp<<endl);
|
||||
// Twice, as we need to detect, then propagate
|
||||
CdcEitherVertex* markp = traceAsyncRecurse(vvertexp, 1, false);
|
||||
if (markp) { // Mark is non-NULL if something bad on this path
|
||||
UINFO(9, " Trace One bad! "<<vvertexp<<endl);
|
||||
traceAsyncRecurse(vvertexp, 2, true);
|
||||
m_graph.userClearVertices(); // user1: bool - was analyzed
|
||||
dumpAsync(vvertexp, markp);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
CdcEitherVertex* CdcVisitor::traceAsyncRecurse(CdcEitherVertex* vertexp, uint32_t did_value, bool mark) {
|
||||
// Return vertex of any dangerous stuff attached, or NULL if OK
|
||||
// If mark, also mark the output even if nothing dangerous below
|
||||
CdcEitherVertex* mark_outp = NULL;
|
||||
UINFO(9," Trace: "<<vertexp<<endl);
|
||||
|
||||
if (vertexp->user()>=did_value) return false; // Processed - prevent loop
|
||||
vertexp->user(did_value);
|
||||
|
||||
if (CdcLogicVertex* vvertexp = dynamic_cast<CdcLogicVertex*>(vertexp)) {
|
||||
// Any logic considered bad, at the moment, anyhow
|
||||
if (!vvertexp->safe() && !mark_outp) mark_outp = vvertexp;
|
||||
// And keep tracing back so the user can understand what's up
|
||||
}
|
||||
else if (CdcVarVertex* vvertexp = dynamic_cast<CdcVarVertex*>(vertexp)) {
|
||||
if (mark) vvertexp->asyncPath(true);
|
||||
// If primary I/O, it's ok here back
|
||||
if (vvertexp->varScp()->varp()->isInput()) return false;
|
||||
// Also ok if from flop
|
||||
if (vvertexp->fromFlop()) return false;
|
||||
}
|
||||
|
||||
for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
|
||||
CdcEitherVertex* eFromVertexp = (CdcEitherVertex*)edgep->fromp();
|
||||
CdcEitherVertex* submarkp = traceAsyncRecurse(eFromVertexp, did_value, mark);
|
||||
if (submarkp && !mark_outp) mark_outp = submarkp;
|
||||
}
|
||||
|
||||
if (mark) vertexp->asyncPath(true);
|
||||
return mark_outp;
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
void CdcVisitor::dumpAsync(CdcVarVertex* vertexp, CdcEitherVertex* markp) {
|
||||
AstNode* nodep = vertexp->varScp();
|
||||
*m_ofp<<"\n";
|
||||
*m_ofp<<"\n";
|
||||
AstNode* targetp = vertexp->nodep();
|
||||
if (V3GraphEdge* edgep = vertexp->outBeginp()) {
|
||||
CdcEitherVertex* eToVertexp = (CdcEitherVertex*)edgep->top();
|
||||
targetp = eToVertexp->nodep();
|
||||
}
|
||||
warnAndFile(markp->nodep(),V3ErrorCode::CDCRSTLOGIC,"Logic in path that feeds async reset, via signal: "+nodep->prettyName());
|
||||
*m_ofp<<"Fanout: "<<vertexp->cntAsyncRst()<<" Target: "<<targetp->fileline()<<endl;
|
||||
dumpAsyncRecurse(vertexp," +--", " | ");
|
||||
}
|
||||
|
||||
void CdcVisitor::dumpAsyncRecurse(CdcEitherVertex* vertexp, const string& prefix, const string& blank) {
|
||||
// Return true if any dangerous stuff attached
|
||||
// If mark, also mark the output even if nothing dangerous below
|
||||
if (vertexp->user()) return; // Processed - prevent loop
|
||||
vertexp->user(1);
|
||||
if (!vertexp->asyncPath()) return; // Not part of path
|
||||
|
||||
*m_ofp<<V3OutFile::indentSpaces(40)<<" "<<blank<<"\n";
|
||||
|
||||
// Dump single variable/logic block
|
||||
// See also OrderGraph::loopsVertexCb(V3GraphVertex* vertexp)
|
||||
{
|
||||
AstNode* nodep = vertexp->nodep();
|
||||
string front = pad(40,nodep->fileline()->ascii()+":");
|
||||
front += " "+prefix+" ";
|
||||
if (nodep->castVarScope()) *m_ofp<<front<<"Variable: "<<nodep->prettyName()<<endl;
|
||||
else {
|
||||
V3EmitV::verilogPrefixedTree(nodep, *m_ofp, prefix+" ", true);
|
||||
if (debug()) {
|
||||
CdcDumpVisitor visitor (nodep, m_ofp, front+"DBG: ");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Now do the other logic in the path
|
||||
for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
|
||||
CdcEitherVertex* eFromVertexp = (CdcEitherVertex*)edgep->fromp();
|
||||
dumpAsyncRecurse(eFromVertexp, blank+" +--", blank+" | ");
|
||||
}
|
||||
}
|
||||
|
||||
//######################################################################
|
||||
// Cdc class functions
|
||||
|
||||
void V3Cdc::cdcAll(AstNetlist* nodep) {
|
||||
UINFO(2,__FUNCTION__<<": "<<endl);
|
||||
CdcVisitor visitor (nodep);
|
||||
}
|
||||
37
src/V3Cdc.h
Normal file
37
src/V3Cdc.h
Normal file
@ -0,0 +1,37 @@
|
||||
// -*- C++ -*-
|
||||
//*************************************************************************
|
||||
// DESCRIPTION: Verilator: Break always into sensitivity block domains
|
||||
//
|
||||
// Code available from: http://www.veripool.org/verilator
|
||||
//
|
||||
// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
|
||||
//
|
||||
//*************************************************************************
|
||||
//
|
||||
// Copyright 2003-2010 by Wilson Snyder. This program is free software; you can
|
||||
// redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License
|
||||
// Version 2.0.
|
||||
//
|
||||
// Verilator is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
//*************************************************************************
|
||||
|
||||
#ifndef _V3CDC_H_
|
||||
#define _V3CDC_H_ 1
|
||||
#include "config_build.h"
|
||||
#include "verilatedos.h"
|
||||
#include "V3Error.h"
|
||||
#include "V3Ast.h"
|
||||
|
||||
//============================================================================
|
||||
|
||||
class V3Cdc {
|
||||
public:
|
||||
static void cdcAll(AstNetlist* nodep);
|
||||
};
|
||||
|
||||
#endif // Guard
|
||||
124
src/V3EmitV.cpp
124
src/V3EmitV.cpp
@ -50,7 +50,8 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
|
||||
virtual void puts(const string& str) = 0;
|
||||
virtual void putbs(const string& str) = 0;
|
||||
virtual void putfs(AstNode* nodep, const string& str) = 0;
|
||||
virtual void putfs(AstNode* nodep, const string& str) = 0; // Fileline and node %% mark
|
||||
virtual void putqs(AstNode* nodep, const string& str) = 0; // Fileline quiet w/o %% mark
|
||||
virtual void putsNoTracking(const string& str) = 0;
|
||||
virtual void putsQuoted(const string& str) {
|
||||
// Quote \ and " for use inside C programs
|
||||
@ -68,16 +69,16 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
virtual void visit(AstModule* nodep, AstNUser*) {
|
||||
putfs(nodep, "module "+modClassName(nodep)+";\n");
|
||||
nodep->iterateChildren(*this);
|
||||
putfs(nodep, "endmodule\n");
|
||||
putqs(nodep, "endmodule\n");
|
||||
}
|
||||
virtual void visit(AstNodeFTask* nodep, AstNUser*) {
|
||||
putfs(nodep, nodep->isFunction() ? "function":"task");
|
||||
puts(" ");
|
||||
puts(nodep->name());
|
||||
puts(";\n");
|
||||
putfs(nodep, "begin\n");
|
||||
putqs(nodep, "begin\n"); // Only putfs the first time for each visitor; later for same node is putqs
|
||||
nodep->stmtsp()->iterateAndNext(*this);
|
||||
putfs(nodep, "end\n");
|
||||
putqs(nodep, "end\n");
|
||||
}
|
||||
|
||||
virtual void visit(AstBegin* nodep, AstNUser*) {
|
||||
@ -88,17 +89,17 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
virtual void visit(AstGenerate* nodep, AstNUser*) {
|
||||
putfs(nodep, "generate\n");
|
||||
nodep->iterateChildren(*this);
|
||||
putfs(nodep, "end\n");
|
||||
putqs(nodep, "end\n");
|
||||
}
|
||||
virtual void visit(AstFinal* nodep, AstNUser*) {
|
||||
putfs(nodep, "final begin\n");
|
||||
nodep->iterateChildren(*this);
|
||||
putfs(nodep, "end\n");
|
||||
putqs(nodep, "end\n");
|
||||
}
|
||||
virtual void visit(AstInitial* nodep, AstNUser*) {
|
||||
putfs(nodep,"initial begin\n");
|
||||
nodep->iterateChildren(*this);
|
||||
putfs(nodep, "end\n");
|
||||
putqs(nodep, "end\n");
|
||||
}
|
||||
virtual void visit(AstAlways* nodep, AstNUser*) {
|
||||
putfs(nodep,"always ");
|
||||
@ -106,7 +107,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
else nodep->sensesp()->iterateAndNext(*this);
|
||||
putbs(" begin\n");
|
||||
nodep->bodysp()->iterateAndNext(*this);
|
||||
putfs(nodep,"end\n");
|
||||
putqs(nodep,"end\n");
|
||||
}
|
||||
virtual void visit(AstNodeAssign* nodep, AstNUser*) {
|
||||
nodep->lhsp()->iterateAndNext(*this);
|
||||
@ -139,7 +140,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
putfs(nodep,"@(");
|
||||
for (AstNode* expp=nodep->sensesp(); expp; expp = expp->nextp()) {
|
||||
expp->accept(*this);
|
||||
if (expp->nextp()) putfs(expp->nextp()," or ");
|
||||
if (expp->nextp()) putqs(expp->nextp()," or ");
|
||||
}
|
||||
puts(")");
|
||||
}
|
||||
@ -165,7 +166,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
}
|
||||
}
|
||||
nodep->itemsp()->iterateAndNext(*this);
|
||||
putfs(nodep,"endcase\n");
|
||||
putqs(nodep,"endcase\n");
|
||||
}
|
||||
virtual void visit(AstCaseItem* nodep, AstNUser*) {
|
||||
if (nodep->condsp()) {
|
||||
@ -173,7 +174,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
} else putbs("default");
|
||||
putfs(nodep,": begin ");
|
||||
nodep->bodysp()->iterateAndNext(*this);
|
||||
putfs(nodep,"end\n");
|
||||
putqs(nodep,"end\n");
|
||||
}
|
||||
virtual void visit(AstComment* nodep, AstNUser*) {
|
||||
puts((string)"// "+nodep->name()+"\n");
|
||||
@ -253,7 +254,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
m_suppressSemi = false;
|
||||
puts(") begin\n");
|
||||
nodep->bodysp()->iterateAndNext(*this);
|
||||
putfs(nodep,"end\n");
|
||||
putqs(nodep,"end\n");
|
||||
}
|
||||
virtual void visit(AstRepeat* nodep, AstNUser*) {
|
||||
putfs(nodep,"repeat (");
|
||||
@ -277,11 +278,11 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
puts(") begin\n");
|
||||
nodep->ifsp()->iterateAndNext(*this);
|
||||
if (nodep->elsesp()) {
|
||||
putfs(nodep,"end\n");
|
||||
putfs(nodep,"else begin\n");
|
||||
putqs(nodep,"end\n");
|
||||
putqs(nodep,"else begin\n");
|
||||
nodep->elsesp()->iterateAndNext(*this);
|
||||
}
|
||||
putfs(nodep,"end\n");
|
||||
putqs(nodep,"end\n");
|
||||
}
|
||||
virtual void visit(AstStop* nodep, AstNUser*) {
|
||||
putfs(nodep,"$stop;\n");
|
||||
@ -437,12 +438,12 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
// Terminals
|
||||
virtual void visit(AstVarRef* nodep, AstNUser*) {
|
||||
putfs(nodep,nodep->hiername());
|
||||
puts(nodep->varp()->name());
|
||||
puts(nodep->varp()->prettyName());
|
||||
}
|
||||
virtual void visit(AstVarXRef* nodep, AstNUser*) {
|
||||
putfs(nodep,nodep->dotted());
|
||||
puts(".");
|
||||
puts(nodep->varp()->name());
|
||||
puts(nodep->varp()->prettyName());
|
||||
}
|
||||
virtual void visit(AstConst* nodep, AstNUser*) {
|
||||
putfs(nodep,nodep->num().ascii(true,true));
|
||||
@ -458,13 +459,13 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
|
||||
virtual void visit(AstVar* nodep, AstNUser*) {
|
||||
putfs(nodep,nodep->verilogKwd());
|
||||
puts(" ");
|
||||
nodep->dtypep()->iterateChildren(*this); puts(" ");
|
||||
nodep->dtypep()->iterateAndNext(*this); puts(" ");
|
||||
puts(nodep->name());
|
||||
puts(";\n");
|
||||
}
|
||||
virtual void visit(AstActive* nodep, AstNUser*) {
|
||||
m_sensesp = nodep->sensesp();
|
||||
nodep->iterateChildren(*this);
|
||||
nodep->stmtsp()->iterateAndNext(*this);
|
||||
m_sensesp = NULL;
|
||||
}
|
||||
virtual void visit(AstVarScope*, AstNUser*) {}
|
||||
@ -501,8 +502,8 @@ class EmitVFileVisitor : public EmitVBaseVisitor {
|
||||
virtual void puts(const string& str) { ofp()->puts(str); }
|
||||
virtual void putbs(const string& str) { ofp()->putbs(str); }
|
||||
virtual void putfs(AstNode*, const string& str) { putbs(str); }
|
||||
virtual void putqs(AstNode*, const string& str) { putbs(str); }
|
||||
virtual void putsNoTracking(const string& str) { ofp()->putsNoTracking(str); }
|
||||
|
||||
public:
|
||||
EmitVFileVisitor(AstNode* nodep, V3OutFile* ofp) {
|
||||
m_ofp = ofp;
|
||||
@ -518,12 +519,12 @@ class EmitVStreamVisitor : public EmitVBaseVisitor {
|
||||
// MEMBERS
|
||||
ostream& m_os;
|
||||
// METHODS
|
||||
virtual void puts(const string& str) { m_os<<str; }
|
||||
virtual void putbs(const string& str) { m_os<<str; }
|
||||
virtual void putfs(AstNode*, const string& str) { putbs(str); }
|
||||
virtual void putsNoTracking(const string& str) { m_os<<str; }
|
||||
|
||||
public:
|
||||
virtual void puts(const string& str) { putsNoTracking(str); }
|
||||
virtual void putbs(const string& str) { puts(str); }
|
||||
virtual void putfs(AstNode*, const string& str) { putbs(str); }
|
||||
virtual void putqs(AstNode*, const string& str) { putbs(str); }
|
||||
public:
|
||||
EmitVStreamVisitor(AstNode* nodep, ostream& os)
|
||||
: m_os(os) {
|
||||
nodep->accept(*this);
|
||||
@ -531,6 +532,75 @@ public:
|
||||
virtual ~EmitVStreamVisitor() {}
|
||||
};
|
||||
|
||||
//######################################################################
|
||||
// Emit to a stream (perhaps stringstream)
|
||||
|
||||
class EmitVPrefixedFormatter : public V3OutFormatter {
|
||||
ostream& m_os;
|
||||
string m_prefix; // What to print at beginning of each line
|
||||
int m_column; // Rough location; need just zero or non-zero
|
||||
FileLine* m_prefixFl;
|
||||
// METHODS
|
||||
virtual void putcOutput(char chr) {
|
||||
if (chr == '\n') {
|
||||
m_column = 0;
|
||||
m_os<<chr;
|
||||
} else {
|
||||
if (m_column == 0) {
|
||||
m_column = 10;
|
||||
m_os<<m_prefixFl->ascii()+":";
|
||||
m_os<<V3OutFile::indentSpaces(40-(m_prefixFl->ascii().length()+1));
|
||||
m_os<<" ";
|
||||
m_os<<m_prefix;
|
||||
}
|
||||
m_column++;
|
||||
m_os<<chr;
|
||||
}
|
||||
}
|
||||
public:
|
||||
void prefixFl(FileLine* fl) { m_prefixFl = fl; }
|
||||
FileLine* prefixFl() const { return m_prefixFl; }
|
||||
int column() const { return m_column; }
|
||||
EmitVPrefixedFormatter(ostream& os, const string& prefix)
|
||||
: V3OutFormatter("__STREAM", true), m_os(os), m_prefix(prefix) {
|
||||
m_column = 0;
|
||||
m_prefixFl = v3Global.rootp()->fileline(); // NETLIST's fileline instead of NULL to avoid NULL checks
|
||||
}
|
||||
virtual ~EmitVPrefixedFormatter() {
|
||||
if (m_column) puts("\n");
|
||||
}
|
||||
};
|
||||
|
||||
class EmitVPrefixedVisitor : public EmitVBaseVisitor {
|
||||
// MEMBERS
|
||||
EmitVPrefixedFormatter m_formatter; // Special verilog formatter (Way down the inheritance is another unused V3OutFormatter)
|
||||
bool m_user3mark; // nodep->user3() if set means mark with %%
|
||||
// METHODS
|
||||
virtual void putsNoTracking(const string& str) { m_formatter.putsNoTracking(str); }
|
||||
virtual void puts(const string& str) { m_formatter.puts(str); }
|
||||
// We don't use m_formatter's putbs because the tokens will change filelines
|
||||
// and insert returns at the proper locations
|
||||
virtual void putbs(const string& str) { m_formatter.puts(str); }
|
||||
virtual void putfs(AstNode* nodep, const string& str) { putfsqs(nodep,str,false); }
|
||||
virtual void putqs(AstNode* nodep, const string& str) { putfsqs(nodep,str,true); }
|
||||
void putfsqs(AstNode* nodep, const string& str, bool quiet) {
|
||||
if (m_formatter.prefixFl() != nodep->fileline()) {
|
||||
m_formatter.prefixFl(nodep->fileline());
|
||||
if (m_formatter.column()) puts("\n"); // This in turn will print the m_prefixFl
|
||||
}
|
||||
if (!quiet && nodep->user3()) puts("%%");
|
||||
putbs(str);
|
||||
}
|
||||
|
||||
public:
|
||||
EmitVPrefixedVisitor(AstNode* nodep, ostream& os, const string& prefix, bool user3mark)
|
||||
: m_formatter(os, prefix), m_user3mark(user3mark) {
|
||||
if (user3mark) { AstUser3InUse::check(); }
|
||||
nodep->accept(*this);
|
||||
}
|
||||
virtual ~EmitVPrefixedVisitor() {}
|
||||
};
|
||||
|
||||
//######################################################################
|
||||
// EmitV class functions
|
||||
|
||||
@ -556,3 +626,7 @@ void V3EmitV::emitv() {
|
||||
void V3EmitV::verilogForTree(AstNode* nodep, ostream& os) {
|
||||
EmitVStreamVisitor(nodep, os);
|
||||
}
|
||||
|
||||
void V3EmitV::verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix, bool user3mark) {
|
||||
EmitVPrefixedVisitor(nodep, os, prefix, user3mark);
|
||||
}
|
||||
|
||||
@ -33,6 +33,7 @@ class V3EmitV {
|
||||
public:
|
||||
static void emitv();
|
||||
static void verilogForTree(AstNode* nodep, ostream& os=cout);
|
||||
static void verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix, bool user3percent);
|
||||
};
|
||||
|
||||
#endif // Guard
|
||||
|
||||
@ -56,6 +56,7 @@ public:
|
||||
CASEOVERLAP, // Case statements overlap
|
||||
CASEWITHX, // Case with X values
|
||||
CASEX, // Casex
|
||||
CDCRSTLOGIC, // Logic in async reset path
|
||||
CMPCONST, // Comparison is constant due to limited range
|
||||
COMBDLY, // Combinatorial delayed assignment
|
||||
STMTDLY, // Delayed statement
|
||||
@ -95,7 +96,7 @@ public:
|
||||
// Warnings
|
||||
" FIRST_WARN",
|
||||
"BLKANDNBLK",
|
||||
"CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CMPCONST",
|
||||
"CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CDCRSTLOGIC", "CMPCONST",
|
||||
"COMBDLY", "STMTDLY", "SYMRSVDWORD", "GENCLK", "IMPERFECTSCH", "IMPLICIT", "IMPURE",
|
||||
"LITENDIAN",
|
||||
"MULTIDRIVEN", "REDEFMACRO",
|
||||
@ -185,7 +186,8 @@ inline void v3errorEnd(ostringstream& sstr) { V3Error::v3errorEnd(sstr); }
|
||||
|
||||
// These allow errors using << operators: v3error("foo"<<"bar");
|
||||
// Careful, you can't put () around msg, as you would in most macro definitions
|
||||
#define v3warn(code,msg) v3errorEnd(((V3Error::v3errorPrep(V3ErrorCode::code)<<msg),V3Error::v3errorStr()));
|
||||
#define v3warnCode(code,msg) v3errorEnd(((V3Error::v3errorPrep(code)<<msg),V3Error::v3errorStr()));
|
||||
#define v3warn(code,msg) v3warnCode(V3ErrorCode::code,msg)
|
||||
#define v3info(msg) v3warn(INFO,msg)
|
||||
#define v3fatal(msg) v3warn(FATAL,msg)
|
||||
#define v3error(msg) v3warn(ERROR,msg)
|
||||
|
||||
@ -269,9 +269,11 @@ const char* V3OutFormatter::indentStr(int num) {
|
||||
static char str[MAXSPACE+20];
|
||||
char* cp = str;
|
||||
if (num>MAXSPACE) num=MAXSPACE;
|
||||
while (num>=8) {
|
||||
*cp++ = '\t';
|
||||
num -= 8;
|
||||
if (!m_verilog) { // verilogPrefixedTree doesn't want tabs
|
||||
while (num>=8) {
|
||||
*cp++ = '\t';
|
||||
num -= 8;
|
||||
}
|
||||
}
|
||||
while (num>0) {
|
||||
*cp++ = ' ';
|
||||
|
||||
@ -100,7 +100,7 @@ private:
|
||||
stack<int> m_parenVec; // Stack of columns where last ( was
|
||||
|
||||
int endLevels(const char* strg);
|
||||
static const char* indentStr(int levels);
|
||||
const char* indentStr(int levels);
|
||||
void putcNoTracking(char chr);
|
||||
|
||||
public:
|
||||
|
||||
@ -122,6 +122,12 @@ private:
|
||||
nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
|
||||
}
|
||||
|
||||
virtual void visit(AstUdpTable* nodep, AstNUser*) {
|
||||
if (!v3Global.opt.bboxUnsup()) {
|
||||
nodep->v3error("Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables.");
|
||||
}
|
||||
}
|
||||
|
||||
// Save some time
|
||||
virtual void visit(AstNodeAssign*, AstNUser*) {}
|
||||
virtual void visit(AstAlways*, AstNUser*) {}
|
||||
|
||||
@ -340,7 +340,8 @@ private:
|
||||
virtual void visit(AstUdpTable* nodep, AstNUser*) {
|
||||
UINFO(5,"UDPTABLE "<<nodep<<endl);
|
||||
if (!v3Global.opt.bboxUnsup()) {
|
||||
nodep->v3error("Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables.");
|
||||
// We don't warn until V3Inst, so that UDPs that are in libraries and
|
||||
// never used won't result in any warnings.
|
||||
} else {
|
||||
// Massive hack, just tie off all outputs so our analysis can proceed
|
||||
AstVar* varoutp = NULL;
|
||||
|
||||
@ -660,6 +660,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
|
||||
else if ( onoff (sw, "-bbox-sys", flag/*ref*/) ) { m_bboxSys = flag; }
|
||||
else if ( onoff (sw, "-bbox-unsup", flag/*ref*/) ) { m_bboxUnsup = flag; }
|
||||
else if ( !strcmp (sw, "-cc") ) { m_outFormatOk = true; m_systemC = false; m_systemPerl = false; }
|
||||
else if ( onoff (sw, "-cdc", flag/*ref*/) ) { m_cdc = flag; }
|
||||
else if ( onoff (sw, "-coverage", flag/*ref*/) ) { coverage(flag); }
|
||||
else if ( onoff (sw, "-coverage-line", flag/*ref*/) ){ m_coverageLine = flag; }
|
||||
else if ( onoff (sw, "-coverage-toggle", flag/*ref*/) ){ m_coverageToggle = flag; }
|
||||
|
||||
@ -96,6 +96,7 @@ class V3Options {
|
||||
bool m_autoflush; // main switch: --autoflush
|
||||
bool m_bboxSys; // main switch: --bbox-sys
|
||||
bool m_bboxUnsup; // main switch: --bbox-unsup
|
||||
bool m_cdc; // main switch: --cdc
|
||||
bool m_coverageLine; // main switch: --coverage-block
|
||||
bool m_coverageToggle;// main switch: --coverage-toggle
|
||||
bool m_coverageUser; // main switch: --coverage-func
|
||||
@ -208,6 +209,7 @@ class V3Options {
|
||||
bool autoflush() const { return m_autoflush; }
|
||||
bool bboxSys() const { return m_bboxSys; }
|
||||
bool bboxUnsup() const { return m_bboxUnsup; }
|
||||
bool cdc() const { return m_cdc; }
|
||||
bool coverage() const { return m_coverageLine || m_coverageToggle || m_coverageUser; }
|
||||
bool coverageLine() const { return m_coverageLine; }
|
||||
bool coverageToggle() const { return m_coverageToggle; }
|
||||
|
||||
@ -50,6 +50,7 @@
|
||||
#include "V3EmitV.h"
|
||||
#include "V3Expand.h"
|
||||
#include "V3File.h"
|
||||
#include "V3Cdc.h"
|
||||
#include "V3Gate.h"
|
||||
#include "V3Graph.h"
|
||||
#include "V3GenClk.h"
|
||||
@ -352,6 +353,11 @@ void process () {
|
||||
V3Dead::deadifyAll(v3Global.rootp(), true);
|
||||
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("const.tree"));
|
||||
|
||||
// Clock domain crossing analysis
|
||||
if (v3Global.opt.cdc()) {
|
||||
V3Cdc::cdcAll(v3Global.rootp());
|
||||
}
|
||||
|
||||
// Reorder assignments in pipelined blocks
|
||||
if (v3Global.opt.oReorder()) {
|
||||
V3Split::splitReorderAll(v3Global.rootp());
|
||||
|
||||
25
test_regress/t/t_cdc_async_bad.pl
Executable file
25
test_regress/t/t_cdc_async_bad.pl
Executable file
@ -0,0 +1,25 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2009 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
compile (
|
||||
v_flags => ['--cdc --lint-only'],
|
||||
verilator_make_gcc => 0,
|
||||
fails => 1,
|
||||
expect=>
|
||||
'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: TOP->v.rst2_bad_n
|
||||
%Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message.
|
||||
%Warning-CDCRSTLOGIC: See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
|
||||
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: TOP->v.rst3_bad_n
|
||||
%Error: Exiting due to.*',
|
||||
);
|
||||
|
||||
file_grep ("$Self->{obj_dir}/V$Self->{name}__cdc.txt", qr/CDC Report/);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
72
test_regress/t/t_cdc_async_bad.v
Normal file
72
test_regress/t/t_cdc_async_bad.v
Normal file
@ -0,0 +1,72 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2009 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Outputs
|
||||
q0, q1, q2, q3, q4, q5,
|
||||
// Inputs
|
||||
clk, d, rst0_n
|
||||
);
|
||||
input clk;
|
||||
input d;
|
||||
|
||||
// OK -- from primary
|
||||
input rst0_n;
|
||||
output wire q0;
|
||||
Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
|
||||
|
||||
// OK -- from flop
|
||||
reg rst1_n;
|
||||
always @ (posedge clk) rst1_n <= rst0_n;
|
||||
output wire q1;
|
||||
Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
|
||||
|
||||
// Bad - logic
|
||||
wire rst2_bad_n = rst0_n | rst1_n;
|
||||
output wire q2;
|
||||
Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
|
||||
|
||||
// Bad - logic in submodule
|
||||
wire rst3_bad_n;
|
||||
Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
|
||||
output wire q3;
|
||||
Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
|
||||
|
||||
// OK - bit selection
|
||||
reg [3:0] rst4_n;
|
||||
always @ (posedge clk) rst4_n <= {4{rst0_n}};
|
||||
output wire q4;
|
||||
Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
|
||||
|
||||
// Bad - logic, but waived
|
||||
// verilator lint_off CDCRSTLOGIC
|
||||
wire rst5_waive_n = rst0_n & rst1_n;
|
||||
// verilator lint_on CDCRSTLOGIC
|
||||
output wire q5;
|
||||
Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
|
||||
|
||||
initial begin
|
||||
$display("%%Error: Not a runnable test");
|
||||
$stop;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Flop (
|
||||
input clk,
|
||||
input d,
|
||||
input rst_n,
|
||||
output q);
|
||||
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) q <= 1'b0;
|
||||
else q <= d;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module Sub (input a, b,
|
||||
output z);
|
||||
wire z = a|b;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user