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37 lines
793 B
Systemverilog
37 lines
793 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event e1;
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event e2;
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event e3;
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initial forever begin
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#2
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->e1;
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#2
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->e2;
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#2
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->e3;
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end
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initial begin
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for (int i = 0; i < 10; i++) begin
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@(e1, e2, e3)
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if (!e1.triggered && !e2.triggered && !e3.triggered) $stop;
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`ifdef TEST_VERBOSE
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$write("got event %0d\n", i);
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`endif
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #21 $stop; // timeout
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endmodule
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`ifndef VERILATOR_TIMING
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`error "VERILATOR_TIMING should have been defined as have --timing"
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`endif
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