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31 lines
621 B
Systemverilog
31 lines
621 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer f;
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always @(posedge clk) begin
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if (!$feof(f)) begin
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$display("Doing stuff with file.");
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end
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// Commenting out these two lines fixes the fault
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else begin
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end
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if (!$feof(f)) begin
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end
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else begin
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$display("Not doing stuff with file.");
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end
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end
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endmodule
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