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Cleanup missing copyrights and those on simply copied files. No functional change.

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This commit is contained in:
Wilson Snyder 2023-01-20 20:42:30 -05:00
parent 79f99dddf7
commit 30d6edd2e5
116 changed files with 274 additions and 161 deletions
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3
ci/docker/buildenv/README.rst
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@ -1,3 +1,6 @@
.. Copyright 2003-2023 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
Verilator Build Docker Container
================================

3
ci/docker/run/README.rst
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@ -1,3 +1,6 @@
.. Copyright 2003-2023 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
Verilator Executable Docker Container
=====================================

1
docs/guide/conf.py
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@ -1,6 +1,7 @@
# pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
#
# Configuration file for Verilator's Sphinx documentation builder.
# Copyright 2003-2023 by Wilson Snyder.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
#
# This file only contains overridden options. For a full list:

2
docs/internals.rst
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@ -1876,4 +1876,6 @@ Copyright 2008-2023 by Wilson Snyder. Verilator is free software; you can
redistribute it and/or modify it under the terms of either the GNU Lesser
General Public License Version 3 or the Perl Artistic License Version 2.0.
SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png

2
docs/verilated.dox
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@ -1,4 +1,4 @@
PROJECT_NAME = "Verilog to Routing - ABC"
PROJECT_NAME = "Verilator"
INPUT = ../../include
OUTPUT_DIRECTORY = _build/doxygen/verilated

2
docs/xml.rst
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@ -74,4 +74,6 @@ Copyright 2020-2023 by Wilson Snyder. Verilator is free software; you can
redistribute it and/or modify it under the terms of either the GNU Lesser
General Public License Version 3 or the Perl Artistic License Version 2.0.
SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png

10
src/V3HierBlock.h
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@ -6,15 +6,11 @@
//
//*************************************************************************
//
// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Copyright 2003-2023 by Wilson Snyder. This program is free software; you
// can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
//
// Verilator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************

1
test_regress/t/t_array_index_increment.pl
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@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);

6
test_regress/t/t_array_index_increment.v
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@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk

2
test_regress/t/t_array_query_with.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_assert_clock_event_unsup.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -11,8 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
compile(
expect_filename=>$Self->{golden_filename},
verilator_flags2=> ['--assert'],
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert'],
fails => 1,
);

4
test_regress/t/t_assert_disable_bad.pl
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@ -11,8 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
compile(
expect_filename=>$Self->{golden_filename},
verilator_flags2=> ['--assert'],
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert'],
fails => 1,
);

2
test_regress/t/t_assert_named_property.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_assert_past.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_assert_property_untyped.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_assert_property_untyped_unsup.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -11,8 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
compile(
expect_filename=>$Self->{golden_filename},
verilator_flags2=> ['--assert'],
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert'],
fails => 1,
);

2
test_regress/t/t_assert_recursive_property_unsup.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_assert_sampled.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_bigmem_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by filamoon. This program is free software; you can
# Copyright 2021 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_case_incrdecr.v
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@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t
(/*AUTOARG*/
// Inputs

2
test_regress/t/t_class_assign_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

4
test_regress/t/t_class_fwd_cc.pl
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@ -2,6 +2,10 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);

2
test_regress/t/t_class_member_sens.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_class_param_bad2.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_clk_gate_ext.v
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@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk

2
test_regress/t/t_clk_inp_init.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2018 by Argon Design. This program is free software; you
# Copyright 2018 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the
# GNU Lesser General Public License Version 3 or the Perl Artistic
# License Version 2.0.

2
test_regress/t/t_clocking_sched.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_const_opt.cpp
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@ -1,7 +1,7 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
//
// Copyright 2021 by Yutetsu TAKATSUKASA. This program is free software; you can
// Copyright 2023 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
@ -9,5 +9,5 @@
//
//*************************************************************************
// This function is used to introduce dependency and disturb optimization
extern "C" int fake_dependency() { return 0; }
// Fake dependency to avoid optimization
extern "C" int c_fake_dependency() { return 0; }

6
test_regress/t/t_const_opt.v
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@ -7,7 +7,7 @@
// This function always returns 0, so safe to take bitwise OR with any value.
// Calling this function stops constant folding as Verialtor does not know
// what this function returns.
import "DPI-C" context function int fake_dependency();
import "DPI-C" context function int c_fake_dependency();
module t(/*AUTOARG*/
// Inputs
@ -146,7 +146,7 @@ module bug3182(in, out);
/* verilator lint_off WIDTH */
always @(in)
bit_source = fake_dependency() | in;
bit_source = c_fake_dependency() | in;
wire [5:0] tmp = bit_source; // V3Gate should inline this
wire out = ~(tmp >> 5) & (bit_source == 5'd10);
@ -203,7 +203,7 @@ module bug3445(input wire clk, input wire [31:0] in, output wire out);
st[1] <= st[0];
st[2] <= st[1];
st[3] <= st[2];
zero <= fake_dependency() > 0;
zero <= c_fake_dependency() > 0;
end
logic result0, result1, result2, result3;

5
test_regress/t/t_const_opt_shortcut.cpp
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@ -1,4 +1,9 @@
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <iostream>
extern "C" int import_func0() {
static int c = 0;
return ++c;

2
test_regress/t/t_const_slicesel.v
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@ -2,7 +2,7 @@
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Michael Lefebvre.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);

2
test_regress/t/t_const_slicesel_bad.v
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@ -2,7 +2,7 @@
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Michael Lefebvre.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);

2
test_regress/t/t_continue_do_while_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

1
test_regress/t/t_convert2string.pl
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@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);

1
test_regress/t/t_convert2string.v
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@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Peter Monsson.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/
// Inputs

3
test_regress/t/t_dfg_3817.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Jevin Sweval. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -10,7 +10,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
# test case was causing use-after-free and segfaulting during Verilation
compile();
ok(1);

2
test_regress/t/t_func_const2_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

3
test_regress/t/t_func_const3_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -11,7 +11,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
lint(
v_flags2 => ["--lint-only"],
fails => 1,
expect_filename => $Self->{golden_filename},
);

2
test_regress/t/t_func_const_packed_array_bad.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_func_const_packed_struct_bad.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_func_const_packed_struct_bad2.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_func_const_struct_bad.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_generate_fatal_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Todd Strader. This program is free software; you
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

1
test_regress/t/t_hier_block.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
clean_objs();

1
test_regress/t/t_hier_block.v
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@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA
// SPDX-License-Identifier: Unlicense
`ifdef USE_VLT
`define HIER_BLOCK

12
test_regress/t/t_hier_block0_bad.out
View File

@ -1,12 +1,12 @@
%Error: t/t_hier_block0_bad.v:20:11: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string parameters
%Error: t/t_hier_block0_bad.v:21:11: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string parameters
: ... In instance t
20 | sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0));
21 | sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0));
| ^~~~~~~~
%Error: t/t_hier_block0_bad.v:22:12: 'sub1' has hier_block metacomment, but 'parameter type' is not supported
%Error: t/t_hier_block0_bad.v:23:12: 'sub1' has hier_block metacomment, but 'parameter type' is not supported
: ... In instance t
22 | sub1 #(.T(logic[7:0])) i_sub1(.in(out0), .out(out1));
23 | sub1 #(.T(logic[7:0])) i_sub1(.in(out0), .out(out1));
| ^
%Error: t/t_hier_block0_bad.v:26:42: Cannot access inside hierarchical block
26 | $display("%d %d %d", count, i_sub0.ff, out1);
%Error: t/t_hier_block0_bad.v:27:42: Cannot access inside hierarchical block
27 | $display("%d %d %d", count, i_sub0.ff, out1);
| ^~
%Error: Exiting due to

1
test_regress/t/t_hier_block0_bad.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);

1
test_regress/t/t_hier_block0_bad.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA
// SPDX-License-Identifier: Unlicense
`define HIER_BLOCK /*verilator hier_block*/

12
test_regress/t/t_hier_block1_bad.out
View File

@ -1,16 +1,16 @@
%Warning-HIERBLOCK: t/t_hier_block1_bad.v:15:8: Top module illegally marked hierarchical block, ignoring marking
%Warning-HIERBLOCK: t/t_hier_block1_bad.v:16:8: Top module illegally marked hierarchical block, ignoring marking
: ... In instance t
: ... Suggest remove verilator hier_block on this module
15 | module t (
16 | module t (
| ^
... For warning description see https://verilator.org/warn/HIERBLOCK?v=latest
... Use "/* verilator lint_off HIERBLOCK */" and lint_on around source to disable this message.
%Error: t/t_hier_block1_bad.v:44:32: Modport cannot be used at the hierarchical block boundary
%Error: t/t_hier_block1_bad.v:45:32: Modport cannot be used at the hierarchical block boundary
: ... In instance t.i_sub1
44 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/
45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/
| ^~
%Error: t/t_hier_block1_bad.v:44:52: Modport cannot be used at the hierarchical block boundary
%Error: t/t_hier_block1_bad.v:45:52: Modport cannot be used at the hierarchical block boundary
: ... In instance t.i_sub1
44 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/
45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/
| ^~~
%Error: Exiting due to

1
test_regress/t/t_hier_block1_bad.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);

1
test_regress/t/t_hier_block1_bad.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA
// SPDX-License-Identifier: Unlicense
`define HIER_BLOCK /*verilator hier_block*/

1
test_regress/t/t_hier_block_cmake.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# If a test fails, broken .cmake may disturb the next run
clean_objs();

1
test_regress/t/t_hier_block_libmod.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt_all => 1);

1
test_regress/t/t_hier_block_libmod.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA
// SPDX-License-Identifier: Unlicense
module t;
t_flag_relinc_sub i_t_flag_relinc_sub();

1
test_regress/t/t_hier_block_nohier.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# This test makes sure that the internal check of t_hier_block.v is correct.
# --hierarchical option is not set intentionally.

1
test_regress/t/t_hier_block_prot_lib.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
top_filename("t/t_hier_block.v");

1
test_regress/t/t_hier_block_prot_lib_shared.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
top_filename("t/t_hier_block.v");

1
test_regress/t/t_hier_block_sc.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
clean_objs();

1
test_regress/t/t_hier_block_sc_trace_fst.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
clean_objs();

1
test_regress/t/t_hier_block_sc_trace_vcd.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
clean_objs();

1
test_regress/t/t_hier_block_trace_fst.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt_all => 1);

1
test_regress/t/t_hier_block_trace_vcd.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt_all => 1);

1
test_regress/t/t_hier_block_vlt.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
clean_objs();

1
test_regress/t/t_hier_block_vlt.vlt
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA
// SPDX-License-Identifier: Unlicense
`verilator_config
hier_block -module "sub?"

1
test_regress/t/t_hier_bynum.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt_all => 1);

1
test_regress/t/t_hier_bynum.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: Unlicense
module flop (q, d, clk);
// No AUTOARG; order of below is different from port order above

6
test_regress/t/t_if_swap.v
View File

@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t
(/*AUTOARG*/
// Inputs

32
test_regress/t/t_increment_bad.out
View File

@ -1,26 +1,26 @@
%Error-UNSUPPORTED: t/t_increment_bad.v:15:31: Unsupported: Incrementation in this context.
15 | if (0 && test_string[pos++] != "e");
%Error-UNSUPPORTED: t/t_increment_bad.v:21:31: Unsupported: Incrementation in this context.
21 | if (0 && test_string[pos++] != "e");
| ^~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_increment_bad.v:16:19: Unsupported: Incrementation in this context.
16 | if (1 || pos-- != 1);
%Error-UNSUPPORTED: t/t_increment_bad.v:22:19: Unsupported: Incrementation in this context.
22 | if (1 || pos-- != 1);
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:18:17: Unsupported: Incrementation in this context.
18 | if (a <-> --b);
%Error-UNSUPPORTED: t/t_increment_bad.v:24:17: Unsupported: Incrementation in this context.
24 | if (a <-> --b);
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:19:16: Unsupported: Incrementation in this context.
19 | if (0 -> ++b);
%Error-UNSUPPORTED: t/t_increment_bad.v:25:16: Unsupported: Incrementation in this context.
25 | if (0 -> ++b);
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:21:24: Unsupported: Incrementation in this context.
21 | pos = (a > 0) ? a++ : --b;
%Error-UNSUPPORTED: t/t_increment_bad.v:27:24: Unsupported: Incrementation in this context.
27 | pos = (a > 0) ? a++ : --b;
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:21:29: Unsupported: Incrementation in this context.
21 | pos = (a > 0) ? a++ : --b;
%Error-UNSUPPORTED: t/t_increment_bad.v:27:29: Unsupported: Incrementation in this context.
27 | pos = (a > 0) ? a++ : --b;
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:23:24: Unsupported: Incrementation in this context.
23 | pos = array[0][0]++;
%Error-UNSUPPORTED: t/t_increment_bad.v:29:24: Unsupported: Incrementation in this context.
29 | pos = array[0][0]++;
| ^~
%Error-UNSUPPORTED: t/t_increment_bad.v:26:37: Unsupported: Incrementation in this context.
26 | assert property (@(posedge clk) a++ >= 0);
%Error-UNSUPPORTED: t/t_increment_bad.v:32:37: Unsupported: Incrementation in this context.
32 | assert property (@(posedge clk) a++ >= 0);
| ^~
%Error: Exiting due to

1
test_regress/t/t_increment_bad.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);

6
test_regress/t/t_increment_bad.v
View File

@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk

2
test_regress/t/t_jumps_do_while.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_lib_prot_exe_bad.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Yinan Xu. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

1
test_regress/t/t_lint_latch_1.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ a, b, o);
input a;

1
test_regress/t/t_lint_latch_2.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ i, o);

1
test_regress/t/t_lint_latch_3.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ out, out2, in );

1
test_regress/t/t_lint_latch_4.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Julien Margetts (Originally provided by YanJiun)
// SPDX-License-Identifier: Unlicense
module test (
input [2:0] a,

1
test_regress/t/t_lint_latch_5.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer)
// SPDX-License-Identifier: Unlicense
module test
(input logic [1:0] a,

4
test_regress/t/t_lint_latch_bad_2.out
View File

@ -1,6 +1,6 @@
%Warning-LATCH: t/t_lint_latch_bad_2.v:11:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value)
%Warning-LATCH: t/t_lint_latch_bad_2.v:12:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
11 | always_comb
12 | always_comb
| ^~~~~~~~~~~
... For warning description see https://verilator.org/warn/LATCH?v=latest
... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.

1
test_regress/t/t_lint_latch_bad_2.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);

1
test_regress/t/t_lint_latch_bad_2.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ a, b, o);
input a;

4
test_regress/t/t_lint_latch_bad_3.out
View File

@ -1,6 +1,6 @@
%Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
%Warning-LATCH: t/t_lint_latch_bad_3.v:19:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
18 | always_comb
19 | always_comb
| ^~~~~~~~~~~
... For warning description see https://verilator.org/warn/LATCH?v=latest
... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.

1
test_regress/t/t_lint_latch_bad_3.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);

1
test_regress/t/t_lint_latch_bad_3.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ reset, a, b, c, en, o1, o2, o3, o4, o5);
input reset;

2
test_regress/t/t_lint_literal_bad.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you
# Copyright 2017 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

4
test_regress/t/t_lint_nolatch_bad.out
View File

@ -1,5 +1,5 @@
%Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block
11 | always_latch
%Warning-NOLATCH: t/t_lint_nolatch_bad.v:12:4: No latches detected in always_latch block
12 | always_latch
| ^~~~~~~~~~~~
... For warning description see https://verilator.org/warn/NOLATCH?v=latest
... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message.

1
test_regress/t/t_lint_nolatch_bad.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);

1
test_regress/t/t_lint_nolatch_bad.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/ a, b, o);
input a;

4
test_regress/t/t_lint_pinnotfound.pl
View File

@ -2,6 +2,10 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);

6
test_regress/t/t_lint_pragma_protected.v
View File

@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// This part should pass OK
module t_lint_pragma_protected;

74
test_regress/t/t_lint_pragma_protected_bad.out
View File

@ -1,53 +1,53 @@
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:8:17: Unknown '`pragma protect' error
8 | `pragma protect encrypt_agent=123
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:14:17: Unknown '`pragma protect' error
14 | `pragma protect encrypt_agent=123
| ^~~~~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/BADSTDPRAGMA?v=latest
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:10:17: Unknown '`pragma protect' error
10 | `pragma protect encrypt_agent_info
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:16:17: Unknown '`pragma protect' error
16 | `pragma protect encrypt_agent_info
| ^~~~~~~~~~~~~~~~~~
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:23:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:27:17: multiple `pragma protected encoding sections
27 | `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:29:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:33:17: multiple `pragma protected encoding sections
33 | `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:44:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:50:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
... Use "/* verilator lint_off PROTECTED */" and lint_on around source to disable this message.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:51:17: Illegal encoding type for `pragma protected encoding
51 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:57:17: Illegal encoding type for `pragma protected encoding
57 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:51:17: Unsupported: only BASE64 is recognized for `pragma protected encoding
51 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
%Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:57:17: Unsupported: only BASE64 is recognized for `pragma protected encoding
57 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:53:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:54:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
54 | c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:59:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:60:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
60 | c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
| ^
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:55:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
55 | IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:61:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
61 | IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
| ^
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:56:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
56 | aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:62:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
62 | aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
| ^
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:57:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
57 | ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:63:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
63 | ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
| ^
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:58:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
58 | ZCBXb3JrIGFzIG==
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
64 | ZCBXb3JrIGFzIG==
| ^
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:59:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:59:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:63:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: multiple `pragma protected encoding sections
66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:65:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:65:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:69:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:70:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:70:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:17: multiple `pragma protected encoding sections
72 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: line_length must be multiple of 4 for BASE64
66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:17: line_length must be multiple of 4 for BASE64
72 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:68:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:77:1: `pragma is missing a pragma_expression.
77 | `pragma
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:74:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:83:1: `pragma is missing a pragma_expression.
83 | `pragma
| ^~~~~~~
%Error: Exiting due to

6
test_regress/t/t_lint_pragma_protected_bad.v
View File

@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_lint_pragma_protected_err;
// This part should see some failures

2
test_regress/t/t_math_signed_calc.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Raynard Qiao. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_negated_property.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_package_struct.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

1
test_regress/t/t_past_funcs.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);

1
test_regress/t/t_past_funcs.v
View File

@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Peter Monsson.
// SPDX-License-Identifier: Unlicense
module t (/*AUTOARG*/
// Inputs

2
test_regress/t/t_past_strobe.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_pkg_using_dollar_unit_items.pl
View File

@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

6
test_regress/t/t_preproc_str_undef.v
View File

@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define PREFIX_ my_prefix_
`define SUFFIX my_suffix
`define PREFIX_SUFFIX my_prefix_suffix

1
test_regress/t/t_process_redecl.pl
View File

@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);

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