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33 lines
647 B
Systemverilog
33 lines
647 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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logic bist;
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logic [38:0] web;
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logic ceb;
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} mem_t;
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module sub
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(input bist_0,
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input bist_1,
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input bist_2,
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output y
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);
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assign y = bist_0 | bist_1 | bist_2;
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endmodule
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module t
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(input mem_t i_ram_mbist [7:0],
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output y
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);
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sub sub
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(.y,
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.bist_0(i_ram_mbist[0].bist),
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.bist_1(i_ram_mbist[1].bist),
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.bist_2(i_ram_mbist[2].bist)
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);
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endmodule
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