Fix top-level unpacked structure resets (#5221).

Changes

@@ -19,6 +19,7 @@ Verilator 5.027 devel
 * Fix fusing macro arguments to not ignore whitespace (#5061). [Tudor Timi]
 * Fix mis-removing $value$plusargs calls (#5127) (#5137). [Seth Pellegrino]
 * Fix splitting if statements with impure conditions (#5219). [Bartłomiej Chmiel, Antmicro Ltd.]
+* Fix top-level unpacked structure resets (#5221).
 * Fix concurrency for mailbox and semaphores (#5222). [Liam Braun]
 
 

src/V3AstNodeDType.h

@@ -219,6 +219,7 @@ public:
     bool isCompound() const override { return !packed(); }
     // For basicp() we reuse the size to indicate a "fake" basic type of same size
     AstBasicDType* basicp() const override {
+        if (!m_packed) return nullptr;
         return (isFourstate()
                     ? VN_AS(findLogicRangeDType(VNumRange{width() - 1, 0}, width(), numeric()),
                             BasicDType)

src/V3EmitCBase.cpp

@@ -211,11 +211,11 @@ void EmitCBaseVisitorConst::emitVarDecl(const AstVar* nodep, bool asRef) {
         if (nodep->isWide()) puts("," + cvtToStr(nodep->widthWords()));
         puts(");\n");
     } else {
-        // strings and other fundamental c types
+        // Strings and other fundamental C types
         if (nodep->isFuncLocal() && nodep->isString()) {
             const string name = nodep->name();
             const string suffix = V3Task::dpiTemporaryVarSuffix();
-            // string temporary variable for DPI-C needs to be static because c_str() will be
+            // String temporary variable for DPI-C needs to be static because c_str() will be
             // passed to C code and the lifetime of the variable must be long enough. See also
             // Issue 2622.
             const bool beStatic = name.size() >= suffix.size()

test_regress/t/t_cover_toggle.out

@@ -30,7 +30,7 @@
            union {
               real val1;  // TODO use bit [7:0] here
               real val2;  // TODO use bit [3:0] here
-%000001    } utoggle;
+           } utoggle;
         
            const reg aconst = '0;
         

test_regress/t/t_cover_toggle_points.out

@@ -36,8 +36,7 @@
            union {
               real val1;  // TODO use bit [7:0] here
               real val2;  // TODO use bit [3:0] here
-%000001    } utoggle;
--000001  point: comment=utoggle.val1
+           } utoggle;
         
            const reg aconst = '0;
         

test_regress/t/t_debug_emitv.out

@@ -21,7 +21,7 @@ module Vt_debug_emitv_t;
     ???? // ASSOCARRAYDTYPE
     int signed [31:0] 
     ???? // DYNARRAYDTYPE
-    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0] bit [0:0] logic [0:0]  e_t;
+    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0]  e_t;
     typedef struct packed 
     {int signed [31:0]  a;}logic signed [2:0] struct 
     {logic signed [2:0]  a;}logicunion 
@@ -36,7 +36,7 @@ module Vt_debug_emitv_t;
     ???? // ASSOCARRAYDTYPE
     int signed [31:0] 
     ???? // DYNARRAYDTYPE
-    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0] bit [0:0] logic [0:0]  ps_t;
+    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0]  ps_t;
     typedef struct 
     {logic signed [2:0]  a;}logicunion 
     {logic a;}struct packed 
@@ -50,7 +50,7 @@ module Vt_debug_emitv_t;
     ???? // ASSOCARRAYDTYPE
     int signed [31:0] 
     ???? // DYNARRAYDTYPE
-    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0] bit [0:0] logic [0:0]  us_t;
+    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0]  us_t;
     typedef union 
     {logic a;}struct packed 
     {int signed [31:0]  a;}bit [31:0] const struct packed 
@@ -63,7 +63,7 @@ module Vt_debug_emitv_t;
     ???? // ASSOCARRAYDTYPE
     int signed [31:0] 
     ???? // DYNARRAYDTYPE
-    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0] bit [0:0] logic [0:0]  union_t;
+    int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] int signed [31:0] real signedstringIData [31:0] logic signed [31:0] int signed [31:0]  union_t;
     struct packed 
     {int signed [31:0]  a;} ps[0:2];
     struct 

test_regress/t/t_var_top_struct.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;

test_regress/t/t_var_top_struct.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct {
+   logic         bist;
+   logic [38:0]  web;
+   logic         ceb;
+} mem_t;
+
+module sub
+  (input bist_0,
+   input bist_1,
+   input bist_2,
+   output y
+   );
+   assign y = bist_0 | bist_1 | bist_2;
+endmodule
+
+module t
+  (input mem_t i_ram_mbist [7:0],
+   output y
+   );
+   sub sub
+     (.y,
+      .bist_0(i_ram_mbist[0].bist),
+      .bist_1(i_ram_mbist[1].bist),
+      .bist_2(i_ram_mbist[2].bist)
+      );
+endmodule