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64 lines
1.4 KiB
Systemverilog
64 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic[3:0] val[3];
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wire[3:0] #5 net[2];
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logic[1:0] idx1 = 0;
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logic[1:0] idx2 = 0;
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logic[0:0] idx3 = 0;
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event e;
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always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n",
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$time, val[0], val[1], val[2], net[0], net[1]);
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assign {net[0], net[1]} = {val[1], 4'hf-val[1]};
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assign #4 val[1] = val[0];
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assign #6 val[2] = val[0];
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always #10 begin // always so we can use NBA
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val[0] = 1;
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#10 val[0] = 2;
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fork #5 val[0] = 3; join_none
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val[0] = #10 val[0] + 2;
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val[0] <= #10 val[idx1] + 2;
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fork begin #5
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val[0] = 5;
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idx1 = 0;
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idx2 = 0;
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idx3 = 0;
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#40 ->e;
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end join_none
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idx1 = 2;
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idx2 = 3;
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idx3 = 1;
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val[idx1][idx2[idx3+:2]] = #20 1;
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@e val[0] = 8;
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fork begin
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#1 val[0] = 9;
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#2 ->e;
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end join_none
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val[0] = @e val[0] + 2;
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val[0] <= @e val[0] + 2;
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fork begin
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#1 val[0] = 11;
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end join_none
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#2 ->e;
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idx1 = 0;
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idx2 = 0;
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idx3 = 0;
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fork begin #2
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idx1 = 2;
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idx2 = 3;
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idx3 = 1;
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end join_none
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#1 val[idx1[idx3+:2]][idx2] <= @e 1;
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#1 ->e;
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#1 $write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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