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11 lines
303 B
Systemverilog
11 lines
303 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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genvar i;
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for (i = 0; i < 0; i = i + 1) begin end
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endmodule
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