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18 lines
358 B
Systemverilog
18 lines
358 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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int array[2][2];
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initial begin
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foreach (array[i, j, badk, badl]); // bad
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$stop;
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end
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endmodule
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