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41 lines
766 B
Systemverilog
41 lines
766 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int m_n_bits;
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function int get_n_bytes;
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return ((m_n_bits - 1) / 8) + 1;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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int i;
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initial begin
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Cls c;
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c = new;
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c.m_n_bits = 23;
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if (c.get_n_bytes() != 3) $stop;
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i = 1 << c.get_n_bytes();
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if (i != 8) $stop;
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i = 32'h1234 >> c.get_n_bytes();
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if (i != 32'h246) $stop;
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i = 32'shffffffff >>> c.get_n_bytes();
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if (i != 32'hffffffff) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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