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55 lines
1.2 KiB
Systemverilog
55 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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// Not legal to put "static" here, so no warning
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function int f_dunit_static();
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int cnt = 0; // Ok to require "static" here somehday
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return ++cnt;
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endfunction
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// Not legal to put "static" here, so no warning
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task t_dunit_static();
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int cnt = 0; // Ok to require "static" here somehday
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$display("%d", ++cnt);
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endtask
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task t_dunit_static_ok(input int in_ok = 1);
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static int cnt_ok = 0; // No warning here
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$display("%d", ++cnt_ok);
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endtask
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module t (/*AUTOARG*/);
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function int f_implicit_static();
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int cnt = 0;
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return ++cnt;
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endfunction
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task t_implicit_static();
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int cnt = 0;
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$display("%d", ++cnt);
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endtask
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// verilator lint_off IMPLICITSTATIC
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function int f_implicit_but_lint_off();
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int cnt = 0;
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return ++cnt;
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endfunction
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int a, b;
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initial begin
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a = f_dunit_static();
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t_dunit_static();
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t_dunit_static_ok();
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a = f_implicit_static();
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t_implicit_static();
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b = f_implicit_but_lint_off();
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$stop;
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end
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endmodule
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