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44 lines
756 B
Systemverilog
44 lines
756 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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int f = 5;
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task tsk; endtask
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package pkg;
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endpackage
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module subm;
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endmodule
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module submo;
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subm sub2();
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endmodule
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module t;
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submo sub1();
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class Base;endclass
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class Cls extends Base;
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task calltsk;
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super.tsk;
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this.tsk;
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super.f = 8;
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this.f = 8;
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sub1.sub2.tsk;
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pkg::f = 8;
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pkg::tsk();
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sub1.sub2.f = 8;
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sub1.sub2.f.f = 8;
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endtask
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endclass
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Cls obj = new;
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initial begin
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obj.calltsk;
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if (f != 5) $stop;
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end
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endmodule
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