Add error on instances without parenthesis.

Changes

@@ -27,6 +27,7 @@ Verilator 5.029 devel
 * Support named event locals (#5422). [Krzysztof Bieganski, Antmicro Ltd.]
 * Support basic dist constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Support inside array constraints (#5448). [Arkadiusz Kozdra, Antmicro Ltd.]
+* Add error on instances without parenthesis.
 * Add partial coverage symbol and branch data in lcov info files (#5388). [Andrew Nolte]
 * Add method to check if there are VPI callbacks of the given type (#5399). [Kaleb Barrett]
 * Remove warning on unsized numbers exceeding 32-bits.

src/V3LinkCells.cpp

@@ -490,12 +490,13 @@ class LinkCellsVisitor final : public VNVisitor {
                 nodep->addNextHere(varp);
                 nodep->hasIfaceVar(true);
             }
-            if (nodep->hasNoParens()) {
-                nodep->v3error("Interface instantiation "
-                               << nodep->prettyNameQ() << " requires parenthesis\n"
-                               << nodep->warnMore() << "... Suggest use '" << nodep->prettyName()
-                               << "()'");
-            }
+        }
+        if (nodep->hasNoParens()) {
+            // Need in the grammar, otherwise it looks like "id/*data_type*/ id/*new_var*/;"
+            nodep->v3error("Instantiation " << nodep->prettyNameQ()
+                                            << " requires parenthesis (IEEE 1800-2023 23.3.2)\n"
+                                            << nodep->warnMore() << "... Suggest use '"
+                                            << nodep->prettyName() << "()'");
         }
         if (nodep->modp()) {  //
             iterateChildren(nodep);

test_regress/t/t_class_membersel_int.v

@@ -20,5 +20,5 @@ module Sub;
 endmodule
 
 module t;
-   Sub foo;
+   Sub foo();
 endmodule

test_regress/t/t_class_packed.v

@@ -10,11 +10,11 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   //TODO sub #(.WIDTH(1)) w1;
-   //TODO sub #(.WIDTH(2)) w2;
-   //TODO sub #(.WIDTH(3)) w3;
-   //TODO sub #(.WIDTH(4)) w4;
-   sub #(.WIDTH(5)) w5;
+   //TODO sub #(.WIDTH(1)) w1();
+   //TODO sub #(.WIDTH(2)) w2();
+   //TODO sub #(.WIDTH(3)) w3();
+   //TODO sub #(.WIDTH(4)) w4();
+   sub #(.WIDTH(5)) w5();
 
    always @ (posedge clk) begin
       $write("*-* All Finished *-*\n");

test_regress/t/t_event_control_expr.v

@@ -142,7 +142,7 @@ module t(/*AUTOARG*/
 `endif
    `endif
 
-   t_cstmt u_cstmt;
+   t_cstmt u_cstmt();
 
    int cyc = 0;
 

test_regress/t/t_fallback_bad.v

@@ -14,11 +14,11 @@ module subm;
 endmodule
 
 module submo;
-   subm sub2;
+   subm sub2();
 endmodule
 
 module t;
-   submo sub1;
+   submo sub1();
 
    class Base;endclass
    class Cls extends Base;

test_regress/t/t_func_const2_bad.v

@@ -29,7 +29,7 @@ module b8
    c9
    #(.A (A),
      .B (8))
-   c9;
+   c9();
 
 endmodule
 
@@ -39,9 +39,9 @@ module t;
    localparam P14 = f_add2(2, 3, f_add(4, 5));
    //localparam P24 = f_add2(7, 8, 9);
 
-   b8 b8;
-   b8 #(.A (6)) b8_a6;
-   b8 #(.A (7)) b8_a7;
+   b8 b8();
+   b8 #(.A (6)) b8_a6();
+   b8 #(.A (7)) b8_a7();
 
    initial begin
       // Should never get here

test_regress/t/t_func_const3_bad.v

@@ -19,15 +19,15 @@ module b9
    c9
    #(.A (A),
      .B (9))
-   c9;
+   c9();
 
 endmodule
 
 module t;
 
-   b9 b9;
-   b9 #(.A (100)) b900;
-   b9 #(.A (1000)) b9k;
+   b9 b9();
+   b9 #(.A (100)) b900();
+   b9 #(.A (1000)) b9k();
 
    initial begin
       // Should never get here

test_regress/t/t_func_dotted.v

@@ -156,4 +156,4 @@ module b;
 
 endmodule : b
 
-bind ma b u_b[0:1];
+bind ma b u_b[0:1]();

test_regress/t/t_gen_missing.v

@@ -7,9 +7,9 @@
 module t;
    //  verilator lint_off PINMISSING
 `ifdef T_GEN_MISSING_BAD
-   foobar #(.FOO_TYPE(1)) foobar;  // This means we should instatiate missing module
+   foobar #(.FOO_TYPE(1)) foobar();  // This means we should instatiate missing module
 `elsif T_GEN_MISSING
-   foobar #(.FOO_TYPE(0)) foobar;  // This means we should instatiate foo0
+   foobar #(.FOO_TYPE(0)) foobar();  // This means we should instatiate foo0
 `else
  `error "Bad Test"
 `endif

test_regress/t/t_hier_task.v

@@ -5,8 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module mod_a;
-   mod_inner u_inner;
-   mod_a_mon u_a_mon;
+   mod_inner u_inner();
+   mod_a_mon u_a_mon();
 
    initial begin
       bit x;

test_regress/t/t_implements_noninterface_bad.v

@@ -17,5 +17,5 @@ class ClsBad2 extends Icls;
 endclass
 
 module t (/*AUTOARG*/);
-   Cls c;
+   ClsBad2 c;
 endmodule

test_regress/t/t_inc_relink.v

@@ -28,7 +28,7 @@ module C;  // Like above but in a module
 endmodule
 
 module t;  // Actually use those to test relinking
-   C c;
+   C c();
 
    initial begin
       A::t();

test_regress/t/t_inst_paren_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_inst_paren_bad.v:11:8: Instantiation 'sub_inst' requires parenthesis (IEEE 1800-2023 23.3.2)
+                                 : ... Suggest use 'sub_inst()'
+   11 |    sub sub_inst;   
+      |        ^~~~~~~~
+%Error: Exiting due to

test_regress/t/t_inst_paren_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_inst_paren_bad.v

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub;
+endmodule
+
+module t(/*AUTOARG*/);
+   sub sub_inst;  // No ()
+endmodule

test_regress/t/t_interface_paren_missing_bad.out

@@ -1,4 +1,4 @@
-%Error: t/t_interface_paren_missing_bad.v:13:9: Interface instantiation 'intf_i' requires parenthesis
+%Error: t/t_interface_paren_missing_bad.v:13:9: Instantiation 'intf_i' requires parenthesis (IEEE 1800-2023 23.3.2)
                                               : ... Suggest use 'intf_i()'
    13 |    intf intf_i;
       |         ^~~~~~

test_regress/t/t_interface_typo_bad.out

@@ -2,7 +2,7 @@
    14 |    foo_intf foo
       |    ^~~~~~~~
 %Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf'
-   22 |    fo_intf the_foo;
+   22 |    fo_intf the_foo();
       |    ^~~~~~~
 %Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable
    27 |         .foo (the_foo)

test_regress/t/t_interface_typo_bad.v

@@ -19,7 +19,7 @@ endmodule
 module t (/*AUTOARG*/);
    // Intentional typo, compiler should point this out, or that fo_intf does
    // not match foo_intf on the submod port map
-   fo_intf the_foo;
+   fo_intf the_foo();
 
    submod
      submod_inst

test_regress/t/t_math_real_public.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-   sub #(.REAL(2.0)) sub;
+   sub #(.REAL(2.0)) sub();
 endmodule
 
 module sub ();

test_regress/t/t_mod_recurse1.v

@@ -15,13 +15,13 @@ module rec;
 
    generate
       if (DEPTH==1) begin
-         rec #(.DEPTH(DEPTH+1)) sub;
+         rec #(.DEPTH(DEPTH+1)) sub();
       end
       else if (DEPTH==2) begin
-         rec #(.DEPTH(DEPTH+1)) subb;
+         rec #(.DEPTH(DEPTH+1)) subb();
       end
       else if (DEPTH==3) begin
-         bottom #(.DEPTH(DEPTH+1)) bot;
+         bottom #(.DEPTH(DEPTH+1)) bot();
       end
    endgenerate
 endmodule

test_regress/t/t_param_avec.v

@@ -12,9 +12,9 @@ module t (/*AUTOARG*/
    clk
    );
    input clk;
-   sub #(.IDX(0), .CHK(10)) i0;
-   sub #(.IDX(2), .CHK(12)) i2;
-   sub #(.IDX(7), .CHK(17)) i7;
+   sub #(.IDX(0), .CHK(10)) i0();
+   sub #(.IDX(2), .CHK(12)) i2();
+   sub #(.IDX(7), .CHK(17)) i7();
    always @ (posedge clk) begin
       $write("*-* All Finished *-*\n");
       $finish;

test_regress/t/t_param_width_loc_bad.v

@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
    input clk;
 
    // bug1624
-   test #(.param(32'd0)) test_i;
+   test #(.param(32'd0)) test_i();
 
    initial begin
       $write("*-* All Finished *-*\n");

test_regress/t/t_split_var_1_bad.v

@@ -24,8 +24,8 @@ module t();
 
    sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
    sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
-   sub2 i_sub2;
-   sub3 i_sub3;
+   sub2 i_sub2();
+   sub3 i_sub3();
    ifs i_ifs();
 
    function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/,

test_regress/t/t_var_static_assign_decl_bad.v

@@ -139,7 +139,7 @@ module t(input clk);
   endfunction
 
   iface iface();
-  prog prog;
+  prog prog();
 
   logic in;
   no_warn no_warn(.in(in), .clk(clk));