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65 lines
1.4 KiB
Systemverilog
65 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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typedef int my_type;
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class my_class;
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static int a = 1;
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endclass
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function int get_val;
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return 2;
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endfunction
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package my_pkg;
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int my_type_size = $bits(my_type);
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int my_class_a = my_class::a;
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int get_val_result = get_val();
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endpackage
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package overwriting_pkg;
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typedef logic [9:0] my_type;
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class my_class;
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static int a = 2;
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endclass
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function int get_val;
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return 3;
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endfunction
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int my_type_size = $bits(my_type);
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int my_class_a = my_class::a;
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int get_val_result = get_val();
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 2) begin
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`checkh(my_pkg::my_type_size, 32);
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`checkh(my_pkg::my_class_a, 1);
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`checkh(my_pkg::get_val_result, 2);
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`checkh(overwriting_pkg::my_type_size, 10);
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`checkh(overwriting_pkg::my_class_a, 2);
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`checkh(overwriting_pkg::get_val_result, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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