Tests: Rename some tests

test_regress/t/t_package_identifier_bad.out

@@ -0,0 +1,5 @@
+%Error-PKGNODECL: t/t_package_identifier_bad.v:15:20: Package/class 'Bar' not found, and needs to be predeclared (IEEE 1800-2023 26.3)
+   15 |     int baz = Foo::Bar::baz;
+      |                    ^~~
+                  ... For error description see https://verilator.org/warn/PKGNODECL?v=latest
+%Error: Exiting due to

test_regress/t/t_package_identifier_bad.v

@@ -4,13 +4,13 @@
 // any use, without warranty, 2023 by Antmicro Ltd.
 // SPDX-License-Identifier: CC0-1.0
 
-package foo;
+package Foo;
 endpackage
 
-package bar;
+package Bar;
     static int baz;
 endpackage
 
 module t;
-    int baz = foo::bar::baz;
+    int baz = Foo::Bar::baz;
 endmodule

test_regress/t/t_pkg_identifier_bad.out

@@ -1,5 +0,0 @@
-%Error-PKGNODECL: t/t_pkg_identifier_bad.v:15:20: Package/class 'bar' not found, and needs to be predeclared (IEEE 1800-2023 26.3)
-   15 |     int baz = foo::bar::baz;
-      |                    ^~~
-                  ... For error description see https://verilator.org/warn/PKGNODECL?v=latest
-%Error: Exiting due to

test_regress/t/t_width_docs_bad.v

@@ -1,19 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2009 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t;
-   int array[5];
-   bit [1:0] rd_addr;
-   wire int rd_value = read_array[rd_addr];  //<--- Warning
-
-   ok ok();
-endmodule
-
-module ok;
-   int array[5];
-   bit [1:0] rd_addr;
-   wire int rd_value = read_array[{1'b0, rd_addr}];  //<--- Fixed
-endmodule;