verilator/test_regress/t/t_math_countbits_bad.v
2024-10-07 21:44:07 -04:00

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320 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Yossi Nivin.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);
integer count;
assign count = $countbits(32'h123456, '0, '1, 'x, 'z);
endmodule