verilator/test_v/t_param_b.v
Wilson Snyder 2ce30e78a1 Move some test_v tests into test_regress area
git-svn-id: file://localhost/svn/verilator/trunk/verilator@843 77ca24e4-aefa-0310-84f0-b9a241c72d87
2006-12-18 19:49:36 +00:00

23 lines
446 B
Verilog

// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_param_b (/*AUTOARG*/
// Outputs
par, varwidth
);
parameter X = 1;
parameter FIVE = 0; // Overridden
parameter TWO = 2;
output [4:0] par;
output [X:0] varwidth;
wire [4:0] par = X;
wire [X:0] varwidth = (FIVE==5)?TWO:0;
endmodule