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Move some test_v tests into test_regress area

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@843 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2006-12-18 19:49:36 +00:00
parent 3b554f4c5b
commit 2ce30e78a1
26 changed files with 67 additions and 152 deletions
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18
test_regress/t/t_blocking.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

24
test_v/t_blocking.v → test_regress/t/t_blocking.v
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@ -1,19 +1,15 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_blocking(/*AUTOARG*/
// Outputs
passed,
module t (/*AUTOARG*/
// Inputs
clk, reset_l
clk
);
input clk;
input reset_l;
output passed; reg passed; initial passed = 0;
integer _mode; initial _mode=0;
reg [7:0] a;
@ -28,10 +24,9 @@ module t_blocking(/*AUTOARG*/
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk or negedge reset_l) begin // filp-flops with asynchronous reset
if (!reset_l) begin
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
passed <= 0;
end
else begin
_mode <= _mode + 1;
@ -42,7 +37,6 @@ module t_blocking(/*AUTOARG*/
c <= 8'd0;
end
else if (_mode==1) begin
$write("[%0t] t_blocking: Running\n", $time);
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
@ -54,7 +48,6 @@ module t_blocking(/*AUTOARG*/
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
$write("[%0t] t_blocking: Running\n", $time);
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
@ -73,7 +66,8 @@ module t_blocking(/*AUTOARG*/
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("[%0t] t_blocking: Passed\n", $time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
@ -101,7 +95,3 @@ module t_blocking(/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

18
test_regress/t/t_equal.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

15
test_v/t_equal.v → test_regress/t/t_equal.v
View File

@ -1,18 +1,15 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_equal(/*AUTOARG*/
// Outputs
passed,
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
output passed; reg passed; initial passed = 0;
integer _mode;
@ -61,13 +58,9 @@ module t_equal(/*AUTOARG*/
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
$write("[%0t] t_equal: Passed\n", $time);
passed <= 1'b1;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

17
test_v/t.v
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@ -33,11 +33,7 @@ module t (/*AUTOARG*/
// Inputs
.clk (clk));
assign passedv[2] = 1'b1;
t_equal tequal
(.passed (passedv[3]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[3] = 1'b1;
assign passedv[4] = 1'b1;
t_initial tinitial
(.passed (passedv[5]),
@ -65,12 +61,7 @@ module t (/*AUTOARG*/
/*AUTOINST*/
// Inputs
.clk (clk));
t_blocking tblocking
(.passed (passedv[10]),
/*AUTOINST*/
// Inputs
.clk (clk),
.reset_l (reset_l));
assign passedv[10] = 1'b1;
t_clk tclk
(.passed (passedv[11]),
/*AUTOINST*/
@ -111,7 +102,3 @@ module t (/*AUTOARG*/
.fastclk (fastclk));
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_arith.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -147,7 +147,3 @@ module t_arith(/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

4
test_v/t_case.v
View File

@ -196,7 +196,3 @@ module t_case(/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_chg.v
View File

@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -73,7 +73,3 @@ module t_chg_a (/*AUTOARG*/
input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1;
input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1;
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_clk.v
View File

@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -113,7 +113,3 @@ module t_clk (/*AUTOARG*/
.reset_l (reset_l));
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_clk_flop.v
View File

@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -23,7 +23,3 @@ module t_clk_flop (/*AUTOARG*/
always @ (posedge clk) q<=a;
always @ (posedge clk2) q2<=a;
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_clk_two.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -27,7 +27,3 @@ module t_clk_two (/*AUTOARG*/
else count <= count + 1;
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_func.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -41,7 +41,3 @@ module t_func (/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_initial.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -48,7 +48,3 @@ module t_initial(/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_inst.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -127,7 +127,3 @@ module t_inst(/*AUTOARG*/
wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide};
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_inst_a.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -35,7 +35,3 @@ module t_inst_a (/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_inst_b.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -36,7 +36,3 @@ module t_inst_b (/*AUTOARG*/
wire o_com = ~i_com;
endmodule
// Local Variables:
// compile-seqmand: "./vlint t_inst_b.v"
// End:

6
test_v/t_loop.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -60,7 +60,3 @@ module t_loop (/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_mem.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -106,7 +106,3 @@ module t_mem (/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_netlist.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -50,7 +50,3 @@ module t_netlist (/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_param.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -144,7 +144,3 @@ module t_param(/*AUTOARG*/
end
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_param_a.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -25,7 +25,3 @@ module t_param_a (/*AUTOARG*/
.varwidth (varwidth[X:0]));
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_param_b.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -20,7 +20,3 @@ module t_param_b (/*AUTOARG*/
wire [X:0] varwidth = (FIVE==5)?TWO:0;
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

4
test_v/t_rnd.v
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@ -56,7 +56,3 @@ module t_rnd(/*AUTOARG*/
// verilator lint_on UNUSED
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/t_task.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -42,7 +42,3 @@ module t_task (/*AUTOARG*/
endtask
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

6
test_v/top.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -39,7 +39,3 @@ module top (/*AUTOARG*/
.reset_l (reset_l));
endmodule
// Local Variables:
// compile-command: "./vlint __FILE__"
// End:

11
test_v/vlint
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@ -1,11 +0,0 @@
#!/bin/sh
# $Id:$
# DESCRIPTION: Verilator: Invoke linting
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
$DIRPROJECT_PREFIX/bin/vlint --brief \
-f input.vc --filt=STMINI,_NETNM,CWCCXX,CSYBEQ,CSEBEQ,NBAJAM,ITENST,STMFOR \
$*