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146 lines
4.4 KiB
Verilog
146 lines
4.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_param(/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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input clk;
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output passed; reg passed; initial passed = 0;
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reg _ranit;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] par1; // From a1 of t_param_a.v
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wire [4:0] par2; // From a2 of t_param_a.v
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wire [4:0] par3; // From a3 of t_param_a.v
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wire [4:0] par4; // From a4 of t_param_a.v
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wire [1:0] varwidth1; // From a1 of t_param_a.v
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wire [2:0] varwidth2; // From a2 of t_param_a.v
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wire [3:0] varwidth3; // From a3 of t_param_a.v
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wire [3:0] varwidth4; // From a4 of t_param_a.v
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// End of automatics
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/*t_param_a AUTO_TEMPLATE (
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.par (par@[]));
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.varwidth (varwidth@[]));
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*/
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parameter XX = 2'bXX;
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parameter THREE = 3;
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t_param_a #(1,5) a1 (
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// Outputs
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.varwidth (varwidth1[1:0]),
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/*AUTOINST*/
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// Outputs
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.par (par1[4:0])); // Templated
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t_param_a #(2,5) a2 (
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// Outputs
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.varwidth (varwidth2[2:0]),
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/*AUTOINST*/
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// Outputs
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.par (par2[4:0])); // Templated
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t_param_a #(THREE,5) a3 (
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// Outputs
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.varwidth (varwidth3[3:0]),
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/*AUTOINST*/
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// Outputs
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.par (par3[4:0])); // Templated
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t_param_a #(THREE,5) a4 (
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// Outputs
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.varwidth (varwidth4[3:0]),
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/*AUTOINST*/
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// Outputs
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.par (par4[4:0])); // Templated
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parameter THREE_BITS_WIDE = 3'b011;
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parameter THREE_2WIDE = 2'b11;
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parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
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parameter THREEPP_32_WIDE = 2*8*2+3;
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parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide
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// Width propagation doesn't care about LHS vs RHS
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// But the width of a RHS/LHS on a upper node does affect lower nodes;
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// Thus must double-descend in width analysis.
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// VCS 7.0.1 is broken on this test!
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parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop;
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parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop;
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// Parameters assign LHS is affectively width zero.
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parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop;
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parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop;
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// Must be careful about LSB's with extracts
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parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop;
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//
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parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3;
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parameter THREE_32_WIDE = 3%32;
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parameter THIRTYTWO = 2; // Param is 32 bits
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parameter [40:0] WIDEPARAM = 41'h12_3456789a;
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parameter [40:0] WIDEPARAM2 = WIDEPARAM;
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reg [7:0] eightb;
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reg [3:0] fourb;
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wire [7:0] eight = 8'b00010000;
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wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE];
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wire [2:0] threebits = ALSO_THREE_WIDE;
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// surefire lint_off CWCCXX
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initial _ranit = 0;
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always @ (posedge clk) begin
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if (!_ranit) begin
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_ranit <= 1;
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$write("[%0t] t_param: Running\n", $time);
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//
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$write(" %d %d %d\n", par1,par2,par3);
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if (par1!==5'd1) $stop;
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if (par2!==5'd2) $stop;
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if (par3!==5'd3) $stop;
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if (par4!==5'd3) $stop;
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if (varwidth1!==2'd2) $stop;
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if (varwidth2!==3'd2) $stop;
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if (varwidth3!==4'd2) $stop;
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if (varwidth4!==4'd2) $stop;
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if (threebits !== 3'b011) $stop;
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if (eight !== 8'b00010000) $stop;
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if (eight2two !== 2'b10) $stop;
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$write(" Params = %b %b\n %b %b\n",
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THREEPP_32_WIDE,THREEPP_3_WIDE,
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THIRTYTWO, THREEPP_32P_WIDE);
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if (THREEPP_32_WIDE !== 32'h23) $stop;
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if (THREEPP_3_WIDE !== 3'h3) $stop;
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if (THREEPP_32P_WIDE !== 32'h23) $stop;
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if (THIRTYTWO[1:0] !== 2'h2) $stop;
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if (THIRTYTWO !== 32'h2) $stop;
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if (THIRTYTWO !== 2) $stop;
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if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop;
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if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop;
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if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1
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//
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// Example of assignment LHS affecting expression widths.
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// verilator lint_off WIDTH
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// surefire lint_off ASWCMB
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// surefire lint_off ASWCBB
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eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop;
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fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop;
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fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop;
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// verilator lint_on WIDTH
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// surefire lint_on ASWCMB
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// surefire lint_on ASWCBB
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//
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$write("[%0t] t_param: Passed\n", $time);
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passed <= 1'b1;
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end
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end
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endmodule
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