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42 lines
788 B
Systemverilog
42 lines
788 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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typedef struct {
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int fst, snd;
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} pair_t;
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class Cls;
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pair_t p;
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endclass
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pair_t a, b;
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Cls c = new;
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initial begin
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a.fst = 1;
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a.snd = 2;
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b.fst = 3;
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b.snd = 4;
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a = b;
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$display("(%d, %d) (%d, %d)", a.fst, a.snd, b.fst, b.snd);
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$display("%%p=%p", a);
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c.p.fst = 5;
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if (c.p.fst != 5) $stop;
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a = c.p;
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if (a.fst != 5) $stop;
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c.p = b;
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if (c.p.fst != 3) $stop;
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if (c.p.snd != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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