mirror of
https://github.com/verilator/verilator.git
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47 lines
878 B
Plaintext
47 lines
878 B
Plaintext
$date
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Wed Feb 23 00:02:43 2022
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$end
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$version
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fstWriter
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var int 32 " cnt [31:0] $end
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$var parameter 96 # v[0] [95:0] $end
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$var parameter 96 $ v[1] [95:0] $end
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$var parameter 96 % v[2] [95:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
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b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
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b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
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b00000000000000000000000000000000 "
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0!
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$end
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#10
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1!
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b00000000000000000000000000000001 "
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#15
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0!
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#20
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1!
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b00000000000000000000000000000010 "
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#25
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0!
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#30
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1!
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b00000000000000000000000000000011 "
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#35
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0!
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#40
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1!
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