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43 lines
1.4 KiB
Systemverilog
43 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface axi_if;
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logic clk;
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wire rlast;
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wire rvalid;
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clocking cb @(posedge clk);
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inout rlast, rvalid;
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endclocking
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endinterface
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module t;
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axi_if axi_vi();
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initial begin
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axi_vi.clk = 1'b0;
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#1 axi_vi.clk = 1'b1; // triggers line 26
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#1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen)
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#1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen)
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end
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initial begin
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@(negedge axi_vi.rvalid);
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$display("[%0t] rvalid==%b", $time, axi_vi.rvalid);
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$display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1);
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if (axi_vi.rlast === 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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$display("[%0t] rvalid <= 1", $time);
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axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13)
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@(posedge axi_vi.rvalid);
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$display("[%0t] rvalid <= 0", $time);
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axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first
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@(negedge axi_vi.clk);
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$display("[%0t] rlast <= 1", $time);
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axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen
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end
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endmodule
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