Fix driving clocking block in Reactive

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>

src/V3AssertPre.cpp

@@ -216,8 +216,16 @@ private:
                                          skewedReadRefp->cloneTree(false)});
             if (skewp->isZero()) {
                 // Drive the var in Re-NBA (IEEE 1800-2023 14.16)
-                m_clockingp->addNextHere(new AstAlwaysReactive{
-                    flp, new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}, ifp});
+                AstSenTree* senTreep
+                    = new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)};
+                senTreep->addSensesp(
+                    new AstSenItem{flp, VEdgeType::ET_CHANGED, skewedReadRefp->cloneTree(false)});
+                AstCMethodHard* const trigp = new AstCMethodHard{
+                    nodep->fileline(),
+                    new AstVarRef{flp, m_clockingp->ensureEventp(), VAccess::READ}, "isTriggered"};
+                trigp->dtypeSetBit();
+                ifp->condp(new AstLogAnd{flp, ifp->condp()->unlinkFrBack(), trigp});
+                m_clockingp->addNextHere(new AstAlwaysReactive{flp, senTreep, ifp});
             } else if (skewp->fileline()->timingOn()) {
                 // Create a fork so that this AlwaysObserved can be retriggered before the
                 // assignment happens. Also then it can be combo, avoiding the need for creating

test_regress/t/t_clocking_react.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    );
+
+execute(
+    );
+
+ok(1);
+1;

test_regress/t/t_clocking_react.v

@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+interface axi_if;
+   logic clk;
+   wire  rlast;
+   wire  rvalid;
+   clocking cb @(posedge clk);
+      inout rlast, rvalid;
+   endclocking
+endinterface
+
+module t;
+   axi_if axi_vi();
+   initial begin
+      axi_vi.clk = 1'b0;
+      #1 axi_vi.clk = 1'b1; // triggers line 26
+      #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen)
+      #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen)
+   end
+   initial begin
+      @(negedge axi_vi.rvalid);
+      $display("[%0t] rvalid==%b", $time, axi_vi.rvalid);
+      $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1);
+      if (axi_vi.rlast === 1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+   initial begin
+      $display("[%0t] rvalid <= 1", $time);
+      axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13)
+      @(posedge axi_vi.rvalid);
+      $display("[%0t] rvalid <= 0", $time);
+      axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first
+      @(negedge axi_vi.clk);
+      $display("[%0t] rlast <= 1", $time);
+      axi_vi.cb.rlast <= 1'b1;  // assigned on second clk posedge (line 15), shouldn't happen
+   end
+endmodule