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62 lines
2.2 KiB
Systemverilog
62 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkc(expc) \
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do begin \
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if (c !== expc) begin \
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$write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \
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$stop; \
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end \
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a=0; b=0; c=0; \
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end while(0);
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module t (/*AUTOARG*/);
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int a, b, c;
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initial begin
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for (; ; ) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; ; a = a + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; ) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(3);
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for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(7);
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for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(8);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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