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Support 'for' initialization with comma

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This commit is contained in:
Wilson Snyder 2023-04-09 09:56:39 -04:00
parent fff0eb5d88
commit d4bb58630e
5 changed files with 68 additions and 51 deletions
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3
src/verilog.y
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@ -3897,8 +3897,7 @@ for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_dec
for_initializationItemList<nodep>: // IEEE: [for_variable_declaration...]
for_initializationItem { $$ = $1; }
| for_initializationItemList ',' for_initializationItem
{ $$ = $1; BBUNSUP($2, "Unsupported: for loop initialization after the first comma"); }
| for_initializationItemList ',' for_initializationItem { $$ = addNextNull($1, $3); }
;
for_initializationItem<nodep>: // IEEE: variable_assignment + for_variable_declaration

10
test_regress/t/t_for_comma_bad.pl → test_regress/t/t_for_comma.pl
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@ -8,11 +8,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
scenarios(simulator => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
compile(
);
execute(
check_finished => 1,
);
ok(1);

61
test_regress/t/t_for_comma.v Normal file
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@ -0,0 +1,61 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkc(expc) \
do begin \
if (c !== expc) begin \
$write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \
$stop; \
end \
a=0; b=0; c=0; \
end while(0);
module t (/*AUTOARG*/);
int a, b, c;
initial begin
for (; ; ) begin c = c + 1 + a + b; break; end
`checkc(1);
for (; ; a = a + 1) begin c = c + 1 + a + b; break; end
`checkc(1);
for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
`checkc(1);
for (; a < 3; ) begin c = c + 1 + a + b; break; end
`checkc(1);
for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end
`checkc(1);
for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
`checkc(1);
for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
`checkc(2);
for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
`checkc(5);
for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
`checkc(6);
for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
`checkc(2);
for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
`checkc(5);
for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
`checkc(6);
for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
`checkc(2);
for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
`checkc(5);
for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
`checkc(6);
for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
`checkc(3);
for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
`checkc(7);
for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
`checkc(8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

11
test_regress/t/t_for_comma_bad.out
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@ -1,11 +0,0 @@
%Error-UNSUPPORTED: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma
27 | for (integer a=0, integer b=0; a<1; ) ;
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma
28 | for (integer a=0, integer b=0; a<1; a=a+1) ;
| ^
%Error-UNSUPPORTED: t/t_for_comma_bad.v:29:23: Unsupported: for loop initialization after the first comma
29 | for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
| ^
%Error: Exiting due to

34
test_regress/t/t_for_comma_bad.v
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@ -1,34 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
integer a, b;
initial begin
for (; ; ) ;
for (; ; a=a+1) ;
for (; ; a=a+1, b=b+1) ;
for (; a<1; ) ;
for (; a<1; a=a+1) ;
for (; a<1; a=a+1, b=b+1) ;
for (a=0; a<1; ) ;
for (a=0; a<1; a=a+1) ;
for (a=0; a<1; a=a+1, b=b+1) ;
for (integer a=0; a<1; ) ;
for (integer a=0; a<1; a=a+1) ;
for (integer a=0; a<1; a=a+1, b=b+1) ;
for (var integer a=0; a<1; ) ;
for (var integer a=0; a<1; a=a+1) ;
for (var integer a=0; a<1; a=a+1, b=b+1) ;
for (integer a=0, integer b=0; a<1; ) ;
for (integer a=0, integer b=0; a<1; a=a+1) ;
for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule