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44 lines
851 B
Verilog
44 lines
851 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_task (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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input clk;
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output passed; reg passed; initial passed = 0;
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reg [7:0] cyc; initial cyc=0;
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reg set_in_task;
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always @ (posedge clk) begin
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if (cyc == 8'd0) begin
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$write("[%0t] t_task: Starting\n",$time);
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cyc <= 8'd1;
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set_in_task <= 0;
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end
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if (cyc == 8'd1) begin
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cyc <= 8'h2;
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ttask;
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end
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if (cyc == 8'd2) begin
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if (!set_in_task) $stop;
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$write("[%0t] t_task: Passed\n",$time);
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cyc <= 8'hf;
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passed <= 1'b1;
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end
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end
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task ttask;
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begin
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$write("[%0t] t_task: In task\n",$time);
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set_in_task <= 1'b1;
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end
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endtask
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endmodule
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