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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
13 lines
291 B
Verilog
13 lines
291 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`define foo bar
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`ifdef foo
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`ifdef baz `else
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// Test file to make sure includes work;
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integer user_loaded_value;
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`endif
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`endif
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