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599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 |
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| .. | ||
| ex_DIDNOTCONVERGE_faulty.rst | ||
| ex_DIDNOTCONVERGE_msg.rst | ||
| ex_DIDNOTCONVERGE_nodbg_msg.rst | ||
| ex_MULTIDRIVEN_faulty.rst | ||
| ex_MULTIDRIVEN_msg.rst | ||
| ex_STMTDLY_faulty.rst | ||
| ex_STMTDLY_msg.rst | ||
| ex_USERERROR_faulty.rst | ||
| ex_USERERROR_msg.rst | ||
| ex_USERFATAL_faulty.rst | ||
| ex_USERFATAL_msg.rst | ||
| ex_USERINFO_faulty.rst | ||
| ex_USERINFO_msg.rst | ||
| ex_USERWARN_faulty.rst | ||
| ex_USERWARN_msg.rst | ||
| ex_VARHIDDEN_faulty.rst | ||
| ex_VARHIDDEN_msg.rst | ||
| ex_WIDTH_1_faulty.rst | ||
| ex_WIDTH_1_fixed.rst | ||
| ex_WIDTH_1_msg.rst | ||