4 Commits

Author	SHA1	Message	Date
Geza Lore	599d23697d	IEEE compliant scheduler (#3384) ... This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278	2022-05-15 16:03:32 +01:00
Wilson Snyder	2418df7bb2	Commentary	2021-09-17 20:03:45 -04:00
Wilson Snyder	aba3883092	Commentary on MULTIDRIVEN (#2972).	2021-05-19 08:14:14 -04:00
Wilson Snyder	adce7ecf4b	Documentation has been rewritten into a book format.	2021-04-11 18:55:06 -04:00