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124 lines
1.9 KiB
Plaintext
124 lines
1.9 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module topa $end
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$scope module t $end
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$var wire 1 # clk $end
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$var wire 32 $ cyc [31:0] $end
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$var wire 32 % c_trace_on [31:0] $end
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$scope module sub $end
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$var wire 32 & inside_sub_a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module topb $end
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$scope module t $end
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$var wire 1 ( clk $end
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$var wire 32 + cyc [31:0] $end
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$var wire 32 , c_trace_on [31:0] $end
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$var real 64 ) r $end
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$scope module sub $end
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$var wire 32 - inside_sub_a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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0#
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b00000000000000000000000000000001 $
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b00000000000000000000000000000000 %
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0(
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r0 )
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b00000000000000000000000000000001 &
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b00000000000000000000000000000001 +
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b00000000000000000000000000000000 ,
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b00000000000000000000000000000010 -
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#10000
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1#
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b00000000000000000000000000000010 $
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b00000000000000000000000000000011 %
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1(
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r0.1 )
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#15000
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0#
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0(
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#20000
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1#
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b00000000000000000000000000000011 $
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b00000000000000000000000000000100 %
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1(
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r0.2 )
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#25000
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0#
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0(
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#30000
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1#
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b00000000000000000000000000000100 $
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b00000000000000000000000000000101 %
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1(
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r0.3 )
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#35000
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0#
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0(
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#40000
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1#
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b00000000000000000000000000000101 $
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b00000000000000000000000000000110 %
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1(
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r0.4 )
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#45000
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0#
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0(
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#50000
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1#
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b00000000000000000000000000000110 $
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b00000000000000000000000000000111 %
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1(
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r0.5 )
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#55000
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0#
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0(
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#60000
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1#
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b00000000000000000000000000000111 $
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b00000000000000000000000000001000 %
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1(
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r0.6 )
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#65000
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0#
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0(
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#70000
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1#
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b00000000000000000000000000001000 $
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b00000000000000000000000000001001 %
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1(
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r0.7 )
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#75000
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0#
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0(
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#80000
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1#
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b00000000000000000000000000001001 $
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b00000000000000000000000000001010 %
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1(
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r0.7999999999999999 )
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#85000
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0#
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0(
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#90000
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1#
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b00000000000000000000000000001010 $
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b00000000000000000000000000001011 %
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1(
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r0.8999999999999999 )
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#95000
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0#
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0(
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#100000
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1#
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b00000000000000000000000000001011 $
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b00000000000000000000000000001100 %
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1(
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r0.9999999999999999 )
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