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Fix tracing replicated hierarchical models (#5027) (#5029)

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Wilson Snyder 2024-03-30 16:00:52 -04:00 committed by GitHub
parent 1d486e3a59
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34 changed files with 33740 additions and 23929 deletions
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@ -57,6 +57,7 @@ Verilator 5.023 devel
* Fix memory leaks (#5016). [Geza Lore]
* Fix $readmem with missing newline (#5019). [Josse Van Delm]
* Fix internal error on missing pattern key (#5023).
* Fix tracing replicated hierarchical models (#5027).
Verilator 5.022 2024-02-24

4
docs/guide/extensions.rst
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@ -576,6 +576,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;trace_init_task*/
Removed.
In versions before 5.024:
Attached to a DPI import to indicate that function should be called when
initializing tracing. This attribute is indented only to be used
internally in code that Verilator generates when :vlopt:`--lib-create`

31
include/verilated.cpp
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@ -2924,6 +2924,37 @@ const VerilatedScopeNameMap* VerilatedContext::scopeNameMap() VL_MT_SAFE {
return &(impp()->m_impdatap->m_nameMap);
}
//======================================================================
// VerilatedContext:: Methods - trace
void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) VL_MT_SAFE {
VL_DEBUG_IF(VL_DBG_MSGF("+ VerilatedContext::trace\n"););
if (tfp->isOpen()) {
VL_FATAL_MT("", 0, "",
"Testbench C call to 'VerilatedContext::trace()' must not be called"
" after 'VerilatedTrace*::open()'\n");
return;
}
{
// Legacy usage may call {modela}->trace(...) then {modelb}->trace(...)
// So check for and suppress second and later calls
if (tfp->modelConnected()) return;
tfp->modelConnected(true);
}
// We rely on m_ns.m_traceBaseModelCbs being stable when trace() is called
// nope: const VerilatedLockGuard lock{m_mutex};
if (m_ns.m_traceBaseModelCbs.empty())
VL_FATAL_MT("", 0, "",
"Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated"
" with --trace or --trace-vcd option");
for (auto& cbr : m_ns.m_traceBaseModelCbs) cbr(tfp, levels, options);
}
void VerilatedContext::traceBaseModelCbAdd(traceBaseModelCb_t cb) VL_MT_SAFE {
// Model creation registering a callback for when Verilated::trace() called
const VerilatedLockGuard lock{m_mutex};
m_ns.m_traceBaseModelCbs.push_back(cb);
}
//======================================================================
// VerilatedSyms:: Methods

11
include/verilated.h
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@ -101,6 +101,7 @@ class VerilatedScope;
class VerilatedScopeNameMap;
template <class, class>
class VerilatedTrace;
class VerilatedTraceBaseC;
class VerilatedTraceConfig;
class VerilatedVar;
class VerilatedVarNameMap;
@ -347,6 +348,10 @@ class VerilatedContext VL_NOT_FINAL {
friend class VerilatedContextImp;
protected:
// TYPES
using traceBaseModelCb_t
= std::function<void(VerilatedTraceBaseC*, int, int)>; // Type of traceBaseModel callbacks
// MEMBERS
// Slow path variables
mutable VerilatedMutex m_mutex; // Mutex for most s_s/s_ns members
@ -393,6 +398,7 @@ protected:
std::string m_profVltFilename; // +prof+vlt filename
VlOs::DeltaCpuTime m_cpuTimeStart{false}; // CPU time, starts when create first model
VlOs::DeltaWallTime m_wallTimeStart{false}; // Wall time, starts when create first model
std::vector<traceBaseModelCb_t> m_traceBaseModelCbs; // Callbacks to traceRegisterModel
} m_ns;
mutable VerilatedMutex m_argMutex; // Protect m_argVec, m_argVecLoaded
@ -566,6 +572,8 @@ public:
/// Can only be called before the thread pool is created (before first model is added).
void threads(unsigned n);
/// Trace signals in models within the context; called by application code
void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0);
/// Allow traces to at some point be enabled (disables some optimizations)
void traceEverOn(bool flag) VL_MT_SAFE {
if (flag) calcUnusedSigs(true);
@ -624,6 +632,9 @@ public:
static constexpr size_t serialized1Size() VL_PURE { return sizeof(m_s); }
void* serialized1Ptr() VL_MT_UNSAFE { return &m_s; }
// Internal: trace registration
void traceBaseModelCbAdd(traceBaseModelCb_t cb) VL_MT_SAFE;
// Internal: Check magic number
static void checkMagic(const VerilatedContext* contextp);
void selfTestClearMagic() { m_magic = 0x2; }

9
include/verilated_fst_c.h
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@ -192,7 +192,7 @@ class VerilatedFstBuffer VL_NOT_FINAL {
/// Create a FST dump file in C standalone (no SystemC) simulations.
/// Also derived for use in SystemC simulations.
class VerilatedFstC VL_NOT_FINAL {
class VerilatedFstC VL_NOT_FINAL : public VerilatedTraceBaseC {
VerilatedFst m_sptrace; // Trace file being created
// CONSTRUCTORS
@ -208,11 +208,14 @@ public:
// METHODS - User called
/// Return if file is open
bool isOpen() const VL_MT_SAFE { return m_sptrace.isOpen(); }
bool isOpen() const override VL_MT_SAFE { return m_sptrace.isOpen(); }
/// Open a new FST file
virtual void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); }
/// Close dump
void close() VL_MT_SAFE { m_sptrace.close(); }
void close() VL_MT_SAFE {
m_sptrace.close();
modelConnected(false);
}
/// Flush dump
void flush() VL_MT_SAFE { m_sptrace.flush(); }
/// Write one cycle of dump data

19
include/verilated_trace.h
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@ -179,6 +179,21 @@ public:
, m_useFstWriterThread{useFstWriterThread} {}
};
//=============================================================================
// VerilatedTraceBaseC - base class of all Verilated*C trace classes
// Internal use only
class VerilatedTraceBaseC VL_NOT_FINAL {
bool m_modelConnected = false; // Model connected by calling Verilated::trace()
public:
/// True if file currently open
virtual bool isOpen() const VL_MT_SAFE = 0;
// internal use only
bool modelConnected() const VL_MT_SAFE { return m_modelConnected; }
void modelConnected(bool flag) VL_MT_SAFE { m_modelConnected = flag; }
};
//=============================================================================
// VerilatedTrace
@ -205,10 +220,6 @@ private:
friend OffloadBuffer;
struct CallbackRecord final {
// Note: would make these fields const, but some old STL implementations
// (the one in Ubuntu 14.04 with GCC 4.8.4 in particular) use the
// assignment operator on inserting into collections, so they don't work
// with const fields...
union { // The callback
const initCb_t m_initCb;
const dumpCb_t m_dumpCb;

2
include/verilated_vcd_c.cpp
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@ -268,7 +268,7 @@ void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE {
// We add output data to m_writep.
// When it gets nearly full we dump it using this routine which calls write()
// This is much faster than using buffered I/O
if (VL_UNLIKELY(!isOpen())) return;
if (VL_UNLIKELY(!m_isOpen)) return;
const char* wp = m_wrBufp;
while (true) {
const ssize_t remaining = (m_writep - wp);

9
include/verilated_vcd_c.h
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@ -251,7 +251,7 @@ public:
/// Class representing a VCD dump file in C standalone (no SystemC)
/// simulations. Also derived for use in SystemC simulations.
class VerilatedVcdC VL_NOT_FINAL {
class VerilatedVcdC VL_NOT_FINAL : public VerilatedTraceBaseC {
VerilatedVcd m_sptrace; // Trace file being created
// CONSTRUCTORS
@ -267,7 +267,7 @@ public:
// METHODS - User called
/// Return if file is open
bool isOpen() const VL_MT_SAFE { return m_sptrace.isOpen(); }
bool isOpen() const override VL_MT_SAFE { return m_sptrace.isOpen(); }
/// Open a new VCD file
/// This includes a complete header dump each time it is called,
/// just as if this object was deleted and reconstructed.
@ -283,7 +283,10 @@ public:
/// first may be removed. Cat files together to create viewable vcd.
void rolloverSize(size_t size) VL_MT_SAFE { m_sptrace.rolloverSize(size); }
/// Close dump
void close() VL_MT_SAFE { m_sptrace.close(); }
void close() VL_MT_SAFE {
m_sptrace.close();
modelConnected(false);
}
/// Flush dump
void flush() VL_MT_SAFE { m_sptrace.flush(); }
/// Write one cycle of dump data

8
src/V3AstNodeOther.h
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@ -76,7 +76,6 @@ class AstNodeFTask VL_NOT_FINAL : public AstNode {
bool m_dpiContext : 1; // DPI import context
bool m_dpiOpenChild : 1; // DPI import open array child wrapper
bool m_dpiTask : 1; // DPI import task (vs. void function)
bool m_dpiTraceInit : 1; // DPI trace_init
bool m_isConstructor : 1; // Class constructor
bool m_isHideLocal : 1; // Verilog local
bool m_isHideProtected : 1; // Verilog protected
@ -106,7 +105,6 @@ protected:
, m_dpiContext{false}
, m_dpiOpenChild{false}
, m_dpiTask{false}
, m_dpiTraceInit{false}
, m_isConstructor{false}
, m_isHideLocal{false}
, m_isHideProtected{false}
@ -162,8 +160,6 @@ public:
bool dpiOpenChild() const { return m_dpiOpenChild; }
void dpiTask(bool flag) { m_dpiTask = flag; }
bool dpiTask() const { return m_dpiTask; }
void dpiTraceInit(bool flag) { m_dpiTraceInit = flag; }
bool dpiTraceInit() const { return m_dpiTraceInit; }
void isConstructor(bool flag) { m_isConstructor = flag; }
bool isConstructor() const { return m_isConstructor; }
bool isHideLocal() const { return m_isHideLocal; }
@ -630,7 +626,6 @@ class AstCFunc final : public AstNode {
bool m_dpiExportImpl : 1; // DPI export implementation (called from DPI dispatcher via lookup)
bool m_dpiImportPrototype : 1; // This is the DPI import prototype (i.e.: provided by user)
bool m_dpiImportWrapper : 1; // Wrapper for invoking DPI import prototype from generated code
bool m_dpiTraceInit : 1; // DPI trace_init
bool m_needProcess : 1; // Needs access to VlProcess of the caller
bool m_recursive : 1; // Recursive or part of recursion
public:
@ -660,7 +655,6 @@ public:
m_dpiExportImpl = false;
m_dpiImportPrototype = false;
m_dpiImportWrapper = false;
m_dpiTraceInit = false;
m_recursive = false;
}
ASTGEN_MEMBERS_AstCFunc;
@ -734,8 +728,6 @@ public:
void dpiImportPrototype(bool flag) { m_dpiImportPrototype = flag; }
bool dpiImportWrapper() const { return m_dpiImportWrapper; }
void dpiImportWrapper(bool flag) { m_dpiImportWrapper = flag; }
void dpiTraceInit(bool flag) { m_dpiTraceInit = flag; }
bool dpiTraceInit() const { return m_dpiTraceInit; }
bool isCoroutine() const { return m_rtnType == "VlCoroutine"; }
void recursive(bool flag) { m_recursive = flag; }
bool recursive() const { return m_recursive; }

78
src/V3EmitCModel.cpp
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@ -196,8 +196,9 @@ class EmitCModel final : public EmitCFunc {
if (v3Global.opt.trace() || !optSystemC()) {
puts("/// Trace signals in the model; called by application code\n");
puts("void trace(" + v3Global.opt.traceClassBase()
+ "C* tfp, int levels, int options = 0);\n");
// Backward-compatible usage of calling trace() on the model - now part of context
puts("void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) {"
" contextp()->trace(tfp, levels, options); }\n");
}
if (v3Global.opt.trace() && optSystemC()) {
puts("/// SC tracing; avoid overloaded virtual function lint warning\n");
@ -243,6 +244,10 @@ class EmitCModel final : public EmitCFunc {
puts("std::unique_ptr<VerilatedTraceConfig> traceConfig() const override final;\n");
}
ofp()->putsPrivate(true); // private:
puts("// Internal functions - trace registration\n");
puts("void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);\n");
puts("};\n");
ofp()->putsEndGuard();
@ -291,6 +296,10 @@ class EmitCModel final : public EmitCFunc {
puts("{\n");
puts("// Register model with the context\n");
puts("contextp()->addModel(this);\n");
if (v3Global.opt.trace())
puts("contextp()->traceBaseModelCbAdd(\n"
"[this](VerilatedTraceBaseC* tfp, int levels, int options) {"
" traceBaseModel(tfp, levels, options); });\n");
if (optSystemC()) {
// Create sensitivity list for when to evaluate the model.
@ -538,14 +547,10 @@ class EmitCModel final : public EmitCFunc {
+ "(" + topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase()
+ "* tracep);\n");
const CFuncVector traceInitFuncps
= findFuncps([](const AstCFunc* nodep) { return nodep->dpiTraceInit(); });
for (const AstCFunc* const funcp : traceInitFuncps) emitCFuncDecl(funcp, modp);
// ::trace
// ::traceRegisterModel
puts("\n");
putns(modp, "VL_ATTR_COLD void " + topClassName() + "::trace(");
puts(v3Global.opt.traceClassBase() + "C* tfp, int levels, int options) {\n");
putns(modp, "VL_ATTR_COLD void " + topClassName() + "::traceBaseModel(");
puts("VerilatedTraceBaseC* tfp, int levels, int options) {\n");
if (optSystemC()) {
puts(/**/ "if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {\n");
puts(/****/ "vl_fatal(__FILE__, __LINE__, name(), \"" + topClassName()
@ -554,47 +559,20 @@ class EmitCModel final : public EmitCFunc {
"elaboration.\");\n");
puts(/**/ "}");
}
puts(/**/ "if (tfp->isOpen()) {\n");
puts(/**/ "(void)levels; (void)options;\n"); // Prevent unused variable warning
puts(/**/ v3Global.opt.traceClassBase() + "C* const stfp = dynamic_cast<"
+ v3Global.opt.traceClassBase() + "C*>(tfp);\n");
puts(/**/ "if (VL_UNLIKELY(!stfp)) {\n");
puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName()
+ +"::trace()' shall not be called after '" + v3Global.opt.traceClassBase()
+ "C::open()'.\");\n");
+ "::trace()' called on non-" + v3Global.opt.traceClassBase() + "C object;\"\n"
+ "\" use --trace-fst with VerilatedFst object,"
+ " and --trace with VerilatedVcd object\");\n");
puts(/**/ "}\n");
puts(/**/ "(void)levels; (void)options; // Prevent unused variable warning\n");
puts(/**/ "tfp->spTrace()->addModel(this);\n");
puts(/**/ "tfp->spTrace()->addInitCb(&" + protect("trace_init") + ", &(vlSymsp->TOP));\n");
puts(/**/ "stfp->spTrace()->addModel(this);\n");
puts(/**/ "stfp->spTrace()->addInitCb(&" + protect("trace_init")
+ ", &(vlSymsp->TOP));\n");
puts(/**/ topModNameProtected + "__" + protect("trace_register")
+ "(&(vlSymsp->TOP), tfp->spTrace());\n");
if (!traceInitFuncps.empty()) {
puts(/**/ "if (levels > 0) {\n");
puts(/****/ "const QData tfpq = reinterpret_cast<QData>(tfp);\n");
for (const AstCFunc* const funcp : traceInitFuncps) {
// Some hackery to locate handle__V for trace_init_task
// Considered a pragma on the handle, but that still doesn't help us attach it here
string handle = funcp->name();
const size_t wr_len = std::strlen("__Vdpiimwrap_");
UASSERT_OBJ(handle.substr(0, wr_len) == "__Vdpiimwrap_", funcp,
"Strange trace_init_task function name");
handle = "vlSymsp->TOP." + handle.substr(wr_len);
const string::size_type pos = handle.rfind("__DOT__");
UASSERT_OBJ(pos != string::npos, funcp, "Strange trace_init_task function name");
handle = handle.substr(0, pos) + "__DOT__handle___05FV";
puts(funcNameProtect(funcp, modp) + "(" + handle
+ ", tfpq, levels - 1, options);\n");
}
puts(/**/ "}\n");
}
puts("}\n");
}
void emitTraceOffMethods(AstNodeModule* modp) {
putSectionDelimiter("Trace configuration");
// ::trace
puts("\n");
putns(modp, "VL_ATTR_COLD void " + topClassName() + "::trace(");
puts(v3Global.opt.traceClassBase() + "C* tfp, int levels, int options) {\n");
puts(/**/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName()
+ +"::trace()' called on model that was Verilated without --trace option\");\n");
+ "(&(vlSymsp->TOP), stfp->spTrace());\n");
puts("}\n");
}
@ -637,11 +615,7 @@ class EmitCModel final : public EmitCFunc {
emitDestructorImplementation();
emitStandardMethods1(modp);
emitStandardMethods2(modp);
if (v3Global.opt.trace()) {
emitTraceMethods(modp);
} else if (!v3Global.opt.systemC()) {
emitTraceOffMethods(modp);
}
if (v3Global.opt.trace()) emitTraceMethods(modp);
if (v3Global.opt.savable()) emitSerializationFunctions();
VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr);

29
src/V3ProtectLib.cpp
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@ -125,11 +125,6 @@ class ProtectVisitor final : public VNVisitor {
addComment(txtp, fl, "Evaluates the library module's final process");
}
void traceComment(AstTextBlock* txtp, FileLine* fl) {
addComment(txtp, fl, "Enables the library module's tracing");
addComment(txtp, fl, "Only usable when used with called from Verilator");
}
void createSvFile(FileLine* fl, AstNodeModule* modp) {
// Comments
AstTextBlock* const txtp = new AstTextBlock{fl};
@ -202,18 +197,6 @@ class ProtectVisitor final : public VNVisitor {
txtp->addText(fl, "import \"DPI-C\" function void " + m_libName
+ "_protectlib_final(chandle handle__V);\n\n");
if (v3Global.opt.trace() && !v3Global.opt.protectIds()) {
txtp->addText(fl, "`ifdef verilator\n");
traceComment(txtp, fl);
txtp->addText(fl, "import \"DPI-C\" function void " + m_libName
+ "_protectlib_trace(chandle handle__V, "
"chandle tfp, int levels, int options)"
+ " /*verilator trace_init_task*/;\n");
// Note V3EmitCModel.cpp requires the name "handle__V".
txtp->addText(fl, "`endif // verilator\n");
txtp->addText(fl, "\n");
}
// Local variables
// Avoid tracing handle, as it is not a stable value, so breaks vcddiff
// Likewise other internals aren't interesting to the user
@ -404,18 +387,6 @@ class ProtectVisitor final : public VNVisitor {
txtp->addText(fl, /**/ "delete handlep__V;\n");
txtp->addText(fl, "}\n\n");
if (v3Global.opt.trace() && !v3Global.opt.protectIds()) {
traceComment(txtp, fl);
txtp->addText(fl, "void " + m_libName
+ "_protectlib_trace(void* vhandlep__V, void* tfp, int levels, "
"int options) {\n");
castPtr(fl, txtp);
txtp->addText(fl,
/**/ "handlep__V->trace(static_cast<" + v3Global.opt.traceClassBase()
+ "C*>(tfp), levels, options);\n");
txtp->addText(fl, "}\n\n");
}
txtp->addText(fl, "}\n");
m_cfilep->tblockp(txtp);
}

1
src/V3Task.cpp
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@ -1215,7 +1215,6 @@ class TaskVisitor final : public VNVisitor {
cfuncp->dpiContext(nodep->dpiContext());
cfuncp->dpiExportImpl(nodep->dpiExport());
cfuncp->dpiImportWrapper(nodep->dpiImport());
cfuncp->dpiTraceInit(nodep->dpiTraceInit());
cfuncp->recursive(nodep->recursive());
if (nodep->dpiImport() || nodep->dpiExport()) {
cfuncp->isStatic(true);

1
src/verilog.l
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@ -773,7 +773,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
return yVL_TAG; }
"/*verilator timing_off*/" { FL_FWD; PARSEP->lexFileline()->timingOn(false); FL_BRK; }
"/*verilator timing_on*/" { FL_FWD; PARSEP->lexFileline()->timingOn(true); FL_BRK; }
"/*verilator trace_init_task*/" { FL; return yVL_TRACE_INIT_TASK; }
"/*verilator tracing_off*/" { FL_FWD; PARSEP->lexFileline()->tracingOn(false); FL_BRK; }
"/*verilator tracing_on*/" { FL_FWD; PARSEP->lexFileline()->tracingOn(true); FL_BRK; }
"/*verilator unroll_disable*/" { FL; return yVL_UNROLL_DISABLE; }

9
src/verilog.y
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@ -987,7 +987,6 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yVL_SFORMAT "/*verilator sformat*/"
%token<fl> yVL_SPLIT_VAR "/*verilator split_var*/"
%token<strp> yVL_TAG "/*verilator tag*/"
%token<fl> yVL_TRACE_INIT_TASK "/*verilator trace_init_task*/"
%token<fl> yVL_UNROLL_DISABLE "/*verilator unroll_disable*/"
%token<fl> yVL_UNROLL_FULL "/*verilator unroll_full*/"
@ -4729,13 +4728,12 @@ array_methodWith<nodeExprp>:
;
dpi_import_export<nodep>: // ==IEEE: dpi_import_export
yIMPORT yaSTRING dpi_tf_import_propertyE dpi_importLabelE function_prototype dpi_tf_TraceInitE ';'
yIMPORT yaSTRING dpi_tf_import_propertyE dpi_importLabelE function_prototype ';'
{ $$ = $5;
if (*$4 != "") $5->cname(*$4);
$5->dpiContext($3 == iprop_CONTEXT);
$5->dpiPure($3 == iprop_PURE);
$5->dpiImport(true);
$5->dpiTraceInit($6);
GRAMMARP->checkDpiVer($1, *$2); v3Global.dpi(true);
if ($$->prettyName()[0]=='$') SYMP->reinsert($$, nullptr, $$->prettyName()); // For $SysTF overriding
SYMP->reinsert($$); }
@ -4768,11 +4766,6 @@ dpi_tf_import_propertyE<iprop>: // IEEE: [ dpi_function_import_property + dpi_ta
| yPURE { $$ = iprop_PURE; }
;
dpi_tf_TraceInitE<cbool>: // Verilator extension
/* empty */ { $$ = false; }
| yVL_TRACE_INIT_TASK { $$ = true; $<fl>$ = $<fl>1; }
;
//************************************************
// Expressions

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test_regress/t/t_hier_block_sc_trace_fst.out
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test_regress/t/t_hier_block_sc_trace_vcd.out
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test_regress/t/t_hier_block_trace_fst.out
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test_regress/t/t_hier_block_trace_vcd.out
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268
test_regress/t/t_hier_trace.out Normal file
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@ -0,0 +1,268 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$scope module t $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$scope module u0_sub_top $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$upscope $end
$scope module u1_sub_top $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$upscope $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$scope module sub_top $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$scope module u0 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u1 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u2 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u3 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u4 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u5 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u6 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u7 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$scope module sub_top $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$scope module u0 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u1 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u2 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u3 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u4 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u5 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u6 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u7 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u0 $end
$var wire 1 , clk $end
$var wire 1 - reset_l $end
$scope module detail_code $end
$var wire 1 , clk $end
$var wire 1 - reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u1 $end
$var wire 1 / clk $end
$var wire 1 0 reset_l $end
$scope module detail_code $end
$var wire 1 / clk $end
$var wire 1 0 reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u2 $end
$var wire 1 2 clk $end
$var wire 1 3 reset_l $end
$scope module detail_code $end
$var wire 1 2 clk $end
$var wire 1 3 reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u3 $end
$var wire 1 5 clk $end
$var wire 1 6 reset_l $end
$scope module detail_code $end
$var wire 1 5 clk $end
$var wire 1 6 reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u4 $end
$var wire 1 8 clk $end
$var wire 1 9 reset_l $end
$scope module detail_code $end
$var wire 1 8 clk $end
$var wire 1 9 reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u5 $end
$var wire 1 ; clk $end
$var wire 1 < reset_l $end
$scope module detail_code $end
$var wire 1 ; clk $end
$var wire 1 < reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u6 $end
$var wire 1 > clk $end
$var wire 1 ? reset_l $end
$scope module detail_code $end
$var wire 1 > clk $end
$var wire 1 ? reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u7 $end
$var wire 1 A clk $end
$var wire 1 B reset_l $end
$scope module detail_code $end
$var wire 1 A clk $end
$var wire 1 B reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u0 $end
$var wire 1 D clk $end
$var wire 1 E reset_l $end
$scope module detail_code $end
$var wire 1 D clk $end
$var wire 1 E reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u1 $end
$var wire 1 G clk $end
$var wire 1 H reset_l $end
$scope module detail_code $end
$var wire 1 G clk $end
$var wire 1 H reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u2 $end
$var wire 1 J clk $end
$var wire 1 K reset_l $end
$scope module detail_code $end
$var wire 1 J clk $end
$var wire 1 K reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u3 $end
$var wire 1 M clk $end
$var wire 1 N reset_l $end
$scope module detail_code $end
$var wire 1 M clk $end
$var wire 1 N reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u4 $end
$var wire 1 P clk $end
$var wire 1 Q reset_l $end
$scope module detail_code $end
$var wire 1 P clk $end
$var wire 1 Q reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u5 $end
$var wire 1 S clk $end
$var wire 1 T reset_l $end
$scope module detail_code $end
$var wire 1 S clk $end
$var wire 1 T reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u6 $end
$var wire 1 V clk $end
$var wire 1 W reset_l $end
$scope module detail_code $end
$var wire 1 V clk $end
$var wire 1 W reset_l $end
$upscope $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u7 $end
$var wire 1 Y clk $end
$var wire 1 Z reset_l $end
$scope module detail_code $end
$var wire 1 Y clk $end
$var wire 1 Z reset_l $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
0$
0&
0'
0)
0*
0,
0-
0/
00
02
03
05
06
08
09
0;
0<
0>
0?
0A
0B
0D
0E
0G
0H
0J
0K
0M
0N
0P
0Q
0S
0T
0V
0W
0Y
0Z

25
test_regress/t/t_hier_trace.pl Executable file
View File

@ -0,0 +1,25 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace.vlt', '--top-module t', '--hierarchical'],
);
execute(
all_run_flags => ['-j 4'],
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;

67
test_regress/t/t_hier_trace.v Normal file
View File

@ -0,0 +1,67 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module detail_code(
input clk,
input reset_l);
endmodule
module sub_top(
input clk,
input reset_l);
detail_code u0(
.clk(clk),
.reset_l(reset_l)
);
detail_code u1(
.clk(clk),
.reset_l(reset_l)
);
detail_code u2(
.clk(clk),
.reset_l(reset_l)
);
detail_code u3(
.clk(clk),
.reset_l(reset_l)
);
detail_code u4(
.clk(clk),
.reset_l(reset_l)
);
detail_code u5(
.clk(clk),
.reset_l(reset_l)
);
detail_code u6(
.clk(clk),
.reset_l(reset_l)
);
detail_code u7(
.clk(clk),
.reset_l(reset_l)
);
endmodule
module t(
input clk,
input reset_l);
sub_top u0_sub_top(
.clk(clk),
.reset_l(reset_l)
);
sub_top u1_sub_top(
.clk(clk),
.reset_l(reset_l)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

9
test_regress/t/t_hier_trace.vlt Normal file
View File

@ -0,0 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`verilator_config
hier_block -module "detail_code"
hier_block -module "sub_top"

268
test_regress/t/t_hier_trace_noinl.out Normal file
View File

@ -0,0 +1,268 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$scope module t $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$scope module u0_sub_top $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$upscope $end
$scope module u1_sub_top $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$upscope $end
$upscope $end
$var wire 1 # clk $end
$var wire 1 $ reset_l $end
$upscope $end
$scope module top.t.u0_sub_top $end
$scope module sub_top $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$scope module u0 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u1 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u2 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u3 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u4 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u5 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u6 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module u7 $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$upscope $end
$var wire 1 & clk $end
$var wire 1 ' reset_l $end
$upscope $end
$scope module top.t.u1_sub_top $end
$scope module sub_top $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$scope module u0 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u1 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u2 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u3 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u4 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u5 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u6 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module u7 $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$upscope $end
$var wire 1 ) clk $end
$var wire 1 * reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u0 $end
$scope module detail_code $end
$var wire 1 , clk $end
$var wire 1 - reset_l $end
$upscope $end
$var wire 1 , clk $end
$var wire 1 - reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u1 $end
$scope module detail_code $end
$var wire 1 / clk $end
$var wire 1 0 reset_l $end
$upscope $end
$var wire 1 / clk $end
$var wire 1 0 reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u2 $end
$scope module detail_code $end
$var wire 1 2 clk $end
$var wire 1 3 reset_l $end
$upscope $end
$var wire 1 2 clk $end
$var wire 1 3 reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u3 $end
$scope module detail_code $end
$var wire 1 5 clk $end
$var wire 1 6 reset_l $end
$upscope $end
$var wire 1 5 clk $end
$var wire 1 6 reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u4 $end
$scope module detail_code $end
$var wire 1 8 clk $end
$var wire 1 9 reset_l $end
$upscope $end
$var wire 1 8 clk $end
$var wire 1 9 reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u5 $end
$scope module detail_code $end
$var wire 1 ; clk $end
$var wire 1 < reset_l $end
$upscope $end
$var wire 1 ; clk $end
$var wire 1 < reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u6 $end
$scope module detail_code $end
$var wire 1 > clk $end
$var wire 1 ? reset_l $end
$upscope $end
$var wire 1 > clk $end
$var wire 1 ? reset_l $end
$upscope $end
$scope module top.t.u0_sub_top.sub_top.u7 $end
$scope module detail_code $end
$var wire 1 A clk $end
$var wire 1 B reset_l $end
$upscope $end
$var wire 1 A clk $end
$var wire 1 B reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u0 $end
$scope module detail_code $end
$var wire 1 D clk $end
$var wire 1 E reset_l $end
$upscope $end
$var wire 1 D clk $end
$var wire 1 E reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u1 $end
$scope module detail_code $end
$var wire 1 G clk $end
$var wire 1 H reset_l $end
$upscope $end
$var wire 1 G clk $end
$var wire 1 H reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u2 $end
$scope module detail_code $end
$var wire 1 J clk $end
$var wire 1 K reset_l $end
$upscope $end
$var wire 1 J clk $end
$var wire 1 K reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u3 $end
$scope module detail_code $end
$var wire 1 M clk $end
$var wire 1 N reset_l $end
$upscope $end
$var wire 1 M clk $end
$var wire 1 N reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u4 $end
$scope module detail_code $end
$var wire 1 P clk $end
$var wire 1 Q reset_l $end
$upscope $end
$var wire 1 P clk $end
$var wire 1 Q reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u5 $end
$scope module detail_code $end
$var wire 1 S clk $end
$var wire 1 T reset_l $end
$upscope $end
$var wire 1 S clk $end
$var wire 1 T reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u6 $end
$scope module detail_code $end
$var wire 1 V clk $end
$var wire 1 W reset_l $end
$upscope $end
$var wire 1 V clk $end
$var wire 1 W reset_l $end
$upscope $end
$scope module top.t.u1_sub_top.sub_top.u7 $end
$scope module detail_code $end
$var wire 1 Y clk $end
$var wire 1 Z reset_l $end
$upscope $end
$var wire 1 Y clk $end
$var wire 1 Z reset_l $end
$upscope $end
$enddefinitions $end
#0
0#
0$
0&
0'
0)
0*
0,
0-
0/
00
02
03
05
06
08
09
0;
0<
0>
0?
0A
0B
0D
0E
0G
0H
0J
0K
0M
0N
0P
0Q
0S
0T
0V
0W
0Y
0Z

27
test_regress/t/t_hier_trace_noinl.pl Executable file
View File

@ -0,0 +1,27 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_hier_trace.v");
compile(
verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace.vlt', '--top-module t', '--hierarchical', '--fno-inline'],
);
execute(
all_run_flags => ['-j 4'],
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;

1
test_regress/t/t_trace_cat_renew_0100.out
View File

@ -1,6 +1,5 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$scope module t $end

2
test_regress/t/t_trace_noflag_bad.out
View File

@ -1,2 +1,2 @@
%Error: Vt_trace_noflag_bad.cpp:101: 'Vt_trace_noflag_bad::trace()' called on model that was Verilated without --trace option
%Error: Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated with --trace or --trace-vcd option
Aborting...

3
test_regress/t/t_trace_open_wrong_order_bad.out Executable file
View File

@ -0,0 +1,3 @@
%Error: Testbench C call to 'VerilatedContext::trace()' must not be called after 'VerilatedTrace*::open()'
Aborting...

5
test_regress/t/t_trace_open_wrong_order_bad.pl
View File

@ -17,10 +17,9 @@ compile(
);
execute(
fails => 1
fails => 1,
expect_filename => $Self->{golden_filename},
);
file_grep($Self->{run_log_filename}, qr/::trace\(\)' shall not be called after 'VerilatedVcdC::open\(\)'/i);
ok(1);
1;

48
test_regress/t/t_trace_two_dump_cc.out
View File

@ -1,6 +1,5 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module topa $end
$var wire 1 # clk $end
$scope module t $end
@ -12,6 +11,18 @@ $timescale 1ps $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 ( clk $end
$scope module t $end
$var wire 1 ( clk $end
$var wire 32 + cyc [31:0] $end
$var wire 32 , c_trace_on [31:0] $end
$var real 64 ) r $end
$scope module sub $end
$var wire 32 - inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -19,64 +30,99 @@ $enddefinitions $end
1#
b00000000000000000000000000000001 $
b00000000000000000000000000000000 %
1(
r0 )
b00000000000000000000000000000001 &
b00000000000000000000000000000001 +
b00000000000000000000000000000000 ,
b00000000000000000000000000000010 -
#15
0#
0(
#20
1#
b00000000000000000000000000000010 $
b00000000000000000000000000000011 %
1(
r0.1 )
#25
0#
0(
#30
1#
b00000000000000000000000000000011 $
b00000000000000000000000000000100 %
1(
r0.2 )
#35
0#
0(
#40
1#
b00000000000000000000000000000100 $
b00000000000000000000000000000101 %
1(
r0.3 )
#45
0#
0(
#50
1#
b00000000000000000000000000000101 $
b00000000000000000000000000000110 %
1(
r0.4 )
#55
0#
0(
#60
1#
b00000000000000000000000000000110 $
b00000000000000000000000000000111 %
1(
r0.5 )
#65
0#
0(
#70
1#
b00000000000000000000000000000111 $
b00000000000000000000000000001000 %
1(
r0.6 )
#75
0#
0(
#80
1#
b00000000000000000000000000001000 $
b00000000000000000000000000001001 %
1(
r0.7 )
#85
0#
0(
#90
1#
b00000000000000000000000000001001 $
b00000000000000000000000000001010 %
1(
r0.7999999999999999 )
#95
0#
0(
#100
1#
b00000000000000000000000000001010 $
b00000000000000000000000000001011 %
1(
r0.8999999999999999 )
#105
0#
0(
#110
1#
b00000000000000000000000000001011 $
b00000000000000000000000000001100 %
1(
r0.9999999999999999 )

46
test_regress/t/t_trace_two_dump_sc.out
View File

@ -1,6 +1,5 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module topa $end
$scope module t $end
$var wire 1 # clk $end
@ -11,6 +10,17 @@ $timescale 1ps $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$scope module t $end
$var wire 1 ( clk $end
$var wire 32 + cyc [31:0] $end
$var wire 32 , c_trace_on [31:0] $end
$var real 64 ) r $end
$scope module sub $end
$var wire 32 - inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -18,62 +28,96 @@ $enddefinitions $end
0#
b00000000000000000000000000000001 $
b00000000000000000000000000000000 %
0(
r0 )
b00000000000000000000000000000001 &
b00000000000000000000000000000001 +
b00000000000000000000000000000000 ,
b00000000000000000000000000000010 -
#10000
1#
b00000000000000000000000000000010 $
b00000000000000000000000000000011 %
1(
r0.1 )
#15000
0#
0(
#20000
1#
b00000000000000000000000000000011 $
b00000000000000000000000000000100 %
1(
r0.2 )
#25000
0#
0(
#30000
1#
b00000000000000000000000000000100 $
b00000000000000000000000000000101 %
1(
r0.3 )
#35000
0#
0(
#40000
1#
b00000000000000000000000000000101 $
b00000000000000000000000000000110 %
1(
r0.4 )
#45000
0#
0(
#50000
1#
b00000000000000000000000000000110 $
b00000000000000000000000000000111 %
1(
r0.5 )
#55000
0#
0(
#60000
1#
b00000000000000000000000000000111 $
b00000000000000000000000000001000 %
1(
r0.6 )
#65000
0#
0(
#70000
1#
b00000000000000000000000000001000 $
b00000000000000000000000000001001 %
1(
r0.7 )
#75000
0#
0(
#80000
1#
b00000000000000000000000000001001 $
b00000000000000000000000000001010 %
1(
r0.7999999999999999 )
#85000
0#
0(
#90000
1#
b00000000000000000000000000001010 $
b00000000000000000000000000001011 %
1(
r0.8999999999999999 )
#95000
0#
0(
#100000
1#
b00000000000000000000000000001011 $
b00000000000000000000000000001100 %
1(
r0.9999999999999999 )

49
test_regress/t/t_trace_two_dumpfst_cc.out
View File

@ -1,5 +1,5 @@
$date
Wed Feb 23 00:03:30 2022
Sat Mar 30 14:01:55 2024
$end
$version
@ -19,9 +19,26 @@ $var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#10
$dumpvars
b00000000000000000000000000000010 )
r0 (
b00000000000000000000000000000000 '
b00000000000000000000000000000001 &
1%
b00000000000000000000000000000001 $
b00000000000000000000000000000000 #
b00000000000000000000000000000001 "
@ -29,61 +46,91 @@ b00000000000000000000000000000001 "
$end
#15
0!
0%
#20
1%
1!
b00000000000000000000000000000010 "
b00000000000000000000000000000011 #
r0.1 (
#25
0!
0%
#30
1%
1!
r0.2 (
b00000000000000000000000000000100 #
b00000000000000000000000000000011 "
#35
0!
0%
#40
1%
1!
b00000000000000000000000000000100 "
b00000000000000000000000000000101 #
r0.3 (
#45
0!
0%
#50
1%
1!
r0.4 (
b00000000000000000000000000000110 #
b00000000000000000000000000000101 "
#55
0!
0%
#60
1%
1!
b00000000000000000000000000000110 "
b00000000000000000000000000000111 #
r0.5 (
#65
0!
0%
#70
1%
1!
r0.6 (
b00000000000000000000000000001000 #
b00000000000000000000000000000111 "
#75
0!
0%
#80
1%
1!
b00000000000000000000000000001000 "
b00000000000000000000000000001001 #
r0.7 (
#85
0!
0%
#90
1%
1!
r0.7999999999999999 (
b00000000000000000000000000001010 #
b00000000000000000000000000001001 "
#95
0!
0%
#100
1%
1!
b00000000000000000000000000001010 "
b00000000000000000000000000001011 #
r0.8999999999999999 (
#105
0!
0%
#110
1%
1!
r0.9999999999999999 (
b00000000000000000000000000001100 #
b00000000000000000000000000001011 "

48
test_regress/t/t_trace_two_port_cc.out
View File

@ -1,6 +1,5 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module topa $end
$var wire 1 # clk $end
$scope module t $end
@ -12,6 +11,18 @@ $timescale 1ps $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 ( clk $end
$scope module t $end
$var wire 1 ( clk $end
$var wire 32 + cyc [31:0] $end
$var wire 32 , c_trace_on [31:0] $end
$var real 64 ) r $end
$scope module sub $end
$var wire 32 - inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -19,64 +30,99 @@ $enddefinitions $end
1#
b00000000000000000000000000000001 $
b00000000000000000000000000000000 %
1(
r0 )
b00000000000000000000000000000001 &
b00000000000000000000000000000001 +
b00000000000000000000000000000000 ,
b00000000000000000000000000000010 -
#15
0#
0(
#20
1#
b00000000000000000000000000000010 $
b00000000000000000000000000000011 %
1(
r0.1 )
#25
0#
0(
#30
1#
b00000000000000000000000000000011 $
b00000000000000000000000000000100 %
1(
r0.2 )
#35
0#
0(
#40
1#
b00000000000000000000000000000100 $
b00000000000000000000000000000101 %
1(
r0.3 )
#45
0#
0(
#50
1#
b00000000000000000000000000000101 $
b00000000000000000000000000000110 %
1(
r0.4 )
#55
0#
0(
#60
1#
b00000000000000000000000000000110 $
b00000000000000000000000000000111 %
1(
r0.5 )
#65
0#
0(
#70
1#
b00000000000000000000000000000111 $
b00000000000000000000000000001000 %
1(
r0.6 )
#75
0#
0(
#80
1#
b00000000000000000000000000001000 $
b00000000000000000000000000001001 %
1(
r0.7 )
#85
0#
0(
#90
1#
b00000000000000000000000000001001 $
b00000000000000000000000000001010 %
1(
r0.7999999999999999 )
#95
0#
0(
#100
1#
b00000000000000000000000000001010 $
b00000000000000000000000000001011 %
1(
r0.8999999999999999 )
#105
0#
0(
#110
1#
b00000000000000000000000000001011 $
b00000000000000000000000000001100 %
1(
r0.9999999999999999 )

46
test_regress/t/t_trace_two_port_sc.out
View File

@ -1,6 +1,5 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module topa $end
$scope module t $end
$var wire 1 # clk $end
@ -11,6 +10,17 @@ $timescale 1ps $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$scope module t $end
$var wire 1 ( clk $end
$var wire 32 + cyc [31:0] $end
$var wire 32 , c_trace_on [31:0] $end
$var real 64 ) r $end
$scope module sub $end
$var wire 32 - inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -18,62 +28,96 @@ $enddefinitions $end
0#
b00000000000000000000000000000001 $
b00000000000000000000000000000000 %
0(
r0 )
b00000000000000000000000000000001 &
b00000000000000000000000000000001 +
b00000000000000000000000000000000 ,
b00000000000000000000000000000010 -
#10000
1#
b00000000000000000000000000000010 $
b00000000000000000000000000000011 %
1(
r0.1 )
#15000
0#
0(
#20000
1#
b00000000000000000000000000000011 $
b00000000000000000000000000000100 %
1(
r0.2 )
#25000
0#
0(
#30000
1#
b00000000000000000000000000000100 $
b00000000000000000000000000000101 %
1(
r0.3 )
#35000
0#
0(
#40000
1#
b00000000000000000000000000000101 $
b00000000000000000000000000000110 %
1(
r0.4 )
#45000
0#
0(
#50000
1#
b00000000000000000000000000000110 $
b00000000000000000000000000000111 %
1(
r0.5 )
#55000
0#
0(
#60000
1#
b00000000000000000000000000000111 $
b00000000000000000000000000001000 %
1(
r0.6 )
#65000
0#
0(
#70000
1#
b00000000000000000000000000001000 $
b00000000000000000000000000001001 %
1(
r0.7 )
#75000
0#
0(
#80000
1#
b00000000000000000000000000001001 $
b00000000000000000000000000001010 %
1(
r0.7999999999999999 )
#85000
0#
0(
#90000
1#
b00000000000000000000000000001010 $
b00000000000000000000000000001011 %
1(
r0.8999999999999999 )
#95000
0#
0(
#100000
1#
b00000000000000000000000000001011 $
b00000000000000000000000000001100 %
1(
r0.9999999999999999 )

49
test_regress/t/t_trace_two_portfst_cc.out
View File

@ -1,5 +1,5 @@
$date
Wed Feb 23 00:03:49 2022
Sat Mar 30 14:08:31 2024
$end
$version
@ -19,9 +19,26 @@ $var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#10
$dumpvars
b00000000000000000000000000000010 )
r0 (
b00000000000000000000000000000000 '
b00000000000000000000000000000001 &
1%
b00000000000000000000000000000001 $
b00000000000000000000000000000000 #
b00000000000000000000000000000001 "
@ -29,61 +46,91 @@ b00000000000000000000000000000001 "
$end
#15
0!
0%
#20
1%
1!
b00000000000000000000000000000010 "
b00000000000000000000000000000011 #
r0.1 (
#25
0!
0%
#30
1%
1!
r0.2 (
b00000000000000000000000000000100 #
b00000000000000000000000000000011 "
#35
0!
0%
#40
1%
1!
b00000000000000000000000000000100 "
b00000000000000000000000000000101 #
r0.3 (
#45
0!
0%
#50
1%
1!
r0.4 (
b00000000000000000000000000000110 #
b00000000000000000000000000000101 "
#55
0!
0%
#60
1%
1!
b00000000000000000000000000000110 "
b00000000000000000000000000000111 #
r0.5 (
#65
0!
0%
#70
1%
1!
r0.6 (
b00000000000000000000000000001000 #
b00000000000000000000000000000111 "
#75
0!
0%
#80
1%
1!
b00000000000000000000000000001000 "
b00000000000000000000000000001001 #
r0.7 (
#85
0!
0%
#90
1%
1!
r0.7999999999999999 (
b00000000000000000000000000001010 #
b00000000000000000000000000001001 "
#95
0!
0%
#100
1%
1!
b00000000000000000000000000001010 "
b00000000000000000000000000001011 #
r0.8999999999999999 (
#105
0!
0%
#110
1%
1!
r0.9999999999999999 (
b00000000000000000000000000001100 #
b00000000000000000000000000001011 "