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42 lines
860 B
Systemverilog
42 lines
860 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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logic a;
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} Data_t;
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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int cyc = 0;
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localparam int SIZE = 20;
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reg[$clog2(SIZE)-1 : 0] ptr;
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Data_t buffer[SIZE];
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Data_t out;
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reg out1;
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always_ff @( posedge clk ) begin
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int i;
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cyc <= cyc + 1;
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if (cyc == 0) begin
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for (i=0;i<SIZE;i=i+1) begin
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buffer[i].a <= 0;
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end
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end
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else begin
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ptr <= (ptr+1);
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out <= buffer[ptr];
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out1 <= buffer[ptr].a;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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