Fix V3Unknown unpacked struct x-assign (#4934)

docs/CONTRIBUTORS

@@ -189,6 +189,7 @@ Vito Gamberini
 William D. Jones
 Wilson Snyder
 Xi Zhang
+Yan Xu
 Yinan Xu
 Yoda Lee
 Yossi Nivin

src/V3Unknown.cpp

@@ -471,7 +471,9 @@ class UnknownVisitor final : public VNVisitor {
                 VL_DO_DANGLING(condp->deleteTree(), condp);
             } else if (!lvalue
                        // Making a scalar would break if we're making an array
-                       && !VN_IS(nodep->dtypep()->skipRefp(), NodeArrayDType)) {
+                       && !VN_IS(nodep->dtypep()->skipRefp(), NodeArrayDType)
+                       && !(VN_IS(nodep->dtypep()->skipRefp(), NodeUOrStructDType)
+                       && !VN_CAST(nodep->dtypep()->skipRefp(), NodeUOrStructDType)->packed())) {
                 // ARRAYSEL(...) -> COND(LT(bit<maxbit), ARRAYSEL(...), {width{1'bx}})
                 VNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);

test_regress/t/t_struct_unpacked_array.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_struct_unpacked_array.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+
+typedef struct {
+    logic a;
+} Data_t;
+
+module t (/*AUTOARG*/
+    clk
+);
+    input clk;
+    int cyc = 0;
+
+    localparam int SIZE = 20;
+    reg[$clog2(SIZE)-1 : 0] ptr;
+    Data_t buffer[SIZE];
+    Data_t out;
+    reg out1;
+
+    always_ff @( posedge clk ) begin
+        int i;
+        cyc <= cyc + 1;
+        if (cyc == 0) begin
+            for (i=0;i<SIZE;i=i+1) begin
+                buffer[i].a <= 0;
+            end
+        end
+        else begin
+            ptr <= (ptr+1);
+            out <= buffer[ptr];
+            out1 <= buffer[ptr].a;
+            $write("*-* All Finished *-*\n");
+            $finish;
+        end
+    end
+
+endmodule