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38 lines
911 B
Systemverilog
38 lines
911 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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logic [15:0] i16;
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logic [15:0] o16;
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logic [31:0] i32;
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logic [31:0] o32;
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logic [63:0] i64;
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logic [63:0] o64;
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always_comb begin
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o16 = {<<4{i16}};
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o32 = {<<4{i32}};
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o64 = {<<4{i64}};
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end
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initial begin
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i16 = 16'hfade;
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i32 = 32'hcafefade;
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i64 = 64'hdeaddeedcafefade;
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#100ns;
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$display("o16=0x%h i16=0x%h", o16, i16);
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if (o16 != 16'hEDAF) $stop;
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$display("o32=0x%h i32=0x%h", o32, i32);
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if (o32 != 32'hEDAFEFAC) $stop;
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$display("o64=0x%h i64=0x%h", o64, i64);
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if (o64 != 64'hEDAFEFACDEEDDAED) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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