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Fix stream of 32 bit (#4536).

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This commit is contained in:
Wilson Snyder 2023-10-03 22:10:50 -04:00
parent f849073137
commit 537650a2cd
4 changed files with 62 additions and 1 deletions
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@ -17,6 +17,7 @@ Verilator 5.017 devel
* Add warning on interface instantiation without parens (#4094). [Gökçe Aydos]
* Fix constification of $realtobits, $bitstoreal (#4522). [Andrew Nolte]
* Fix conversion of integers in $display '%e' (#4528). [muzafferkal]
* Fix stream of 32 bit (#4536). [Julien Faucher]
* Support randc (#4349).
* Support resizing function call inout arguments (#4467).

2
include/verilated_funcs.h
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@ -1437,7 +1437,7 @@ static inline IData VL_STREAML_FAST_III(int lbits, IData ld, IData rd_log2) VL_P
if (rd_log2) {
const uint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); // max multiple of rd <= lbits
const uint32_t lbitsRem = lbits - lbitsFloor; // number of bits in most-sig slice (MSS)
const IData msbMask = VL_MASK_I(lbitsRem) << lbitsFloor; // mask to sel only bits in MSS
const IData msbMask = lbitsFloor == 32 ? 0UL : VL_MASK_I(lbitsRem) << lbitsFloor;
ret = (ret & ~msbMask) | ((ret & msbMask) << ((VL_UL(1) << rd_log2) - lbitsRem));
}
switch (rd_log2) {

23
test_regress/t/t_stream5.pl Executable file
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@ -0,0 +1,23 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
verilator_flags2 => ["--exe --main --timing"],
make_main => 0,
);
execute(
check_finished => 1,
);
ok(1);
1;

37
test_regress/t/t_stream5.v Normal file
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@ -0,0 +1,37 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);
logic [15:0] i16;
logic [15:0] o16;
logic [31:0] i32;
logic [31:0] o32;
logic [63:0] i64;
logic [63:0] o64;
always_comb begin
o16 = {<<4{i16}};
o32 = {<<4{i32}};
o64 = {<<4{i64}};
end
initial begin
i16 = 16'hfade;
i32 = 32'hcafefade;
i64 = 64'hdeaddeedcafefade;
#100ns;
$display("o16=0x%h i16=0x%h", o16, i16);
if (o16 != 16'hEDAF) $stop;
$display("o32=0x%h i32=0x%h", o32, i32);
if (o32 != 32'hEDAFEFAC) $stop;
$display("o64=0x%h i64=0x%h", o64, i64);
if (o64 != 64'hEDAFEFACDEEDDAED) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule