mirror of
https://github.com/verilator/verilator.git
synced 2025-01-21 05:44:03 +00:00
8 lines
222 B
Systemverilog
8 lines
222 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
(* attr
|