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Tests: Improve some coverage

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This commit is contained in:
Wilson Snyder 2022-11-05 11:40:34 -04:00
parent 6ae6b16223
commit 21926eeb6b
33 changed files with 475 additions and 54 deletions
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2
src/V3Config.cpp
View File

@ -515,7 +515,7 @@ void V3Config::addInline(FileLine* fl, const string& module, const string& ftask
V3ConfigResolver::s().modules().at(module).setInline(on);
} else {
if (!on) {
fl->v3error("no_inline not supported for tasks");
fl->v3error("Unsupported: no_inline for tasks");
} else {
V3ConfigResolver::s().modules().at(module).ftasks().at(ftask).setNoInline(on);
}

2
src/V3Options.cpp
View File

@ -835,7 +835,7 @@ void V3Options::notify() {
}
if (coverage() && savable()) {
cmdfl->v3error("--coverage and --savable not supported together");
cmdfl->v3error("Unsupported: --coverage and --savable not supported together");
}
// Mark options as available

5
src/V3Width.cpp
View File

@ -802,7 +802,7 @@ private:
// Don't need to iterate because V3Const already constified
const int width = nodep->elementsConst();
if (width > (1 << 28)) {
nodep->v3error("Width of bit range is huge; vector of over 1billion bits: 0x"
nodep->v3error("Width of bit range is huge; vector of over 1 billion bits: 0x"
<< std::hex << width);
}
// Note width() not set on range; use elementsConst()
@ -831,7 +831,8 @@ private:
V3Const::constifyParamsEdit(nodep->widthp()); // widthp may change
const AstConst* const widthConstp = VN_CAST(nodep->widthp(), Const);
if (!widthConstp) {
nodep->v3error("Width of bit extract isn't a constant");
nodep->v3error(
"Width of bit extract isn't a constant"); // Impossible? // LCOV_EXCL_LINE
nodep->dtypeSetBit();
return;
}

2
src/V3WidthSel.cpp
View File

@ -499,7 +499,7 @@ private:
warnTri(rhsp);
const int width = VN_AS(widthp, Const)->toSInt();
if (width > (1 << 28)) {
nodep->v3error("Width of :+ or :- is huge; vector of over 1billion bits: "
nodep->v3error("Width of :+ or :- is huge; vector of over 1 billion bits: "
<< widthp->prettyName());
}
if (width < 0) nodep->v3error("Width of :+ or :- is < 0: " << widthp->prettyName());

25
test_regress/t/t_class_member_bad2.out Normal file
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@ -0,0 +1,25 @@
%Error: t/t_class_member_bad2.v:9:8: Duplicate declaration of signal: 'vardup'
9 | int vardup;
| ^~~~~~
t/t_class_member_bad2.v:8:8: ... Location of original declaration
8 | int vardup;
| ^~~~~~
%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of task: 'memdup'
12 | task memdup;
| ^~~~~~
t/t_class_member_bad2.v:10:9: ... Location of original declaration
10 | task memdup;
| ^~~~~~
%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of task: 'funcdup'
17 | function void funcdup;
| ^~~~~~~
t/t_class_member_bad2.v:15:18: ... Location of original declaration
15 | function void funcdup;
| ^~~~~~~
%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of member name: 'memdup'
12 | task memdup;
| ^~~~~~
%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of member name: 'funcdup'
17 | function void funcdup;
| ^~~~~~~
%Error: Exiting due to

19
test_regress/t/t_class_member_bad2.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2020 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

23
test_regress/t/t_class_member_bad2.v Normal file
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@ -0,0 +1,23 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class ClsDup;
int vardup;
int vardup;
task memdup;
endtask
task memdup;
endtask
function void funcdup;
endfunction
function void funcdup;
endfunction
endclass
module t (/*AUTOARG*/);
endmodule

13
test_regress/t/t_class_new_bad.out
View File

@ -10,4 +10,15 @@
: ... In instance t
33 | c3 = new();
| ^~~
%Error: Exiting due to
%Error: t/t_class_new_bad.v:34:12: dynamic new() not expected in this context (data type must be dynamic array)
: ... In instance t
34 | c1 = new[2];
| ^~~
%Error: t/t_class_new_bad.v:34:10: Assign RHS expects a CLASSREFDTYPE 'ClsNoArg'
: ... In instance t
34 | c1 = new[2];
| ^
%Error: Internal Error: t/t_class_new_bad.v:34:10: ../V3Width.cpp:#: Node has no type
: ... In instance t
34 | c1 = new[2];
| ^

1
test_regress/t/t_class_new_bad.v
View File

@ -31,6 +31,7 @@ module t (/*AUTOARG*/);
c1 = new(3); // Bad, called with arg
c2 = new(3); // Bad, called with arg
c3 = new(); // Bad, called without arg
c1 = new[2];
$stop;
end
endmodule

31
test_regress/t/t_dist_warn_coverage.pl
View File

@ -21,14 +21,19 @@ my %Outputs;
my %Suppressed;
foreach my $s (
' exited with ', # driver.pl filters out
' exited with ', # Is hit; driver.pl filters out
'EOF in unterminated string', # Instead get normal unterminated
'Enum ranges must be integral, per spec', # Hard to hit
'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages
'Select from non-array ', # Instead get type does not have a bit range
'Syntax error parsing real: \'', # Instead can't lex the number
'Unsupported: Ranges ignored in port-lists', # Hard to hit
'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error
# Not yet analyzed
' is not an in/out/inout/param/interface: ',
' loading non-variable',
'$fopen mode should be <= 4 characters',
'\'foreach\' loop variable expects simple variable name',
'--coverage and --savable not supported together',
'--pipe-filter protocol error, unexpected: ',
'/*verilator sformat*/ can only be applied to last argument of ',
'Argument needed for string.',
@ -47,10 +52,7 @@ foreach my $s (
'Circular logic when ordering code (non-cutable edge loop)',
'Deferred assertions must use \'#0\' (IEEE 1800-2017 16.4)',
'Define or directive not defined: `',
'Duplicate declaration of member name: ',
'EOF in (*',
'Enum names without values only allowed on numeric types',
'Enum ranges must be integral, per spec',
'Exceeded limit of ',
'Extern declaration\'s scope is not a defined class',
'Format to $display-like function must have constant format string',
@ -73,8 +75,6 @@ foreach my $s (
'Parameter type pin value isn\'t a type: Param ',
'Parameter type variable isn\'t a type: Param ',
'Pattern replication value of 0 is not legal.',
'Return with return value isn\'t underneath a function',
'Select from non-array ',
'Signals inside functions/tasks cannot be marked forceable',
'Size-changing cast to zero or negative size',
'Slice size cannot be zero.',
@ -82,9 +82,7 @@ foreach my $s (
'String of ',
'Symbol matching ',
'Syntax Error: Range \':\', \'+:\' etc are not allowed in the instance ',
'Syntax error parsing real: \'',
'Syntax error: \'virtual\' not allowed before var declaration',
'This may be because there\'s no search path specified with -I<dir>.',
'Unexpected connection to arrayed port',
'Unhandled attribute type',
'Unknown Error Code: ',
@ -101,8 +99,6 @@ foreach my $s (
'Unsupported/unknown built-in dynamic array method ',
'Unsupported: $bits for queue',
'Unsupported: $c can\'t generate wider than 64 bits',
'Unsupported: %l in $fscanf',
'Unsupported: %m in $fscanf',
'Unsupported: --no-structs-packed',
'Unsupported: 4-state numbers in this context',
'Unsupported: Concatenation to form ',
@ -111,7 +107,6 @@ foreach my $s (
'Unsupported: Per-bit array instantiations ',
'Unsupported: Public functions with >64 bit outputs; ',
'Unsupported: RHS of ==? or !=? must be ',
'Unsupported: Ranges ignored in port-lists',
'Unsupported: Replication to form ',
'Unsupported: Shifting of by over 32-bit number isn\'t supported.',
'Unsupported: Signal strengths are unsupported ',
@ -120,19 +115,10 @@ foreach my $s (
'Unsupported: Unclocked assertion',
'Unsupported: don\'t know how to deal with ',
'Unsupported: event arrays',
'Unsupported: left < right of bit extract: ',
'Unsupported: modport export',
'Unsupported: no_inline for tasks',
'Unsupported: static cast to ',
'Unsupported: super',
'Width of :+ or :- is < 0: ',
'Width of :+ or :- is huge; vector of over 1billion bits: ',
'Width of bit extract isn\'t a constant',
'Width of bit range is huge; vector of over 1billion bits: 0x',
'dynamic new() not expected in this context (data type must be dynamic array)',
'dynamic new() not expected in this context (expected under an assign)',
'line_length must be multiple of 4 for BASE64',
'new() not expected in this context',
'no_inline not supported for tasks',
) { $Suppressed{$s} = 1; }
if (!-r "$root/.git") {
@ -153,6 +139,7 @@ sub check {
print "\n";
print "Checking for v3error/v3warn messages in sources without coverage in test_regress/t/*.out:\n";
print "(Developers: If a message is impossible, use UASSERT or v3fatalSrc instead of v3error)";
print "\n";
my %used_suppressed;

17
test_regress/t/t_gen_missing_bad2.out Normal file
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@ -0,0 +1,17 @@
%Error: t/t_gen_missing_bad2.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
: ... In instance t
8 | if ($test$plusargs("BAD-non-constant")) begin
| ^~~~~~~~~~~~~~
%Error: t/t_gen_missing_bad2.v:8:8: Generate If condition must evaluate to constant
: ... In instance t
8 | if ($test$plusargs("BAD-non-constant")) begin
| ^~~~~~~~~~~~~~
%Error: t/t_gen_missing_bad2.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
: ... In instance t
12 | $test$plusargs("BAD-non-constant"): initial $stop;
| ^~~~~~~~~~~~~~
%Error: t/t_gen_missing_bad2.v:12:41: Generate Case item does not evaluate to constant
: ... In instance t
12 | $test$plusargs("BAD-non-constant"): initial $stop;
| ^
%Error: Exiting due to

19
test_regress/t/t_gen_missing_bad2.pl Executable file
View File

@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

15
test_regress/t/t_gen_missing_bad2.v Normal file
View File

@ -0,0 +1,15 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
if ($test$plusargs("BAD-non-constant")) begin
initial $stop;
end
case (1)
$test$plusargs("BAD-non-constant"): initial $stop;
endcase
endmodule

29
test_regress/t/t_gen_nonconst_bad.out
View File

@ -1,17 +1,14 @@
%Error: t/t_gen_nonconst_bad.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
: ... In instance t
8 | if ($test$plusargs("BAD-non-constant")) begin
| ^~~~~~~~~~~~~~
%Error: t/t_gen_nonconst_bad.v:8:8: Generate If condition must evaluate to constant
: ... In instance t
8 | if ($test$plusargs("BAD-non-constant")) begin
| ^~~~~~~~~~~~~~
%Error: t/t_gen_nonconst_bad.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
: ... In instance t
12 | $test$plusargs("BAD-non-constant"): initial $stop;
| ^~~~~~~~~~~~~~
%Error: t/t_gen_nonconst_bad.v:12:41: Generate Case item does not evaluate to constant
: ... In instance t
12 | $test$plusargs("BAD-non-constant"): initial $stop;
| ^
%Error: t/t_gen_nonconst_bad.v:8:4: Cannot find file containing module: 'nfound'
8 | nfound nfound();
| ^~~~~~
%Error: t/t_gen_nonconst_bad.v:8:4: This may be because there's no search path specified with -I<dir>.
8 | nfound nfound();
| ^~~~~~
... Looked in:
nfound
nfound.v
nfound.sv
obj_dir/nfound
obj_dir/nfound.v
obj_dir/nfound.sv
%Error: Exiting due to

4
test_regress/t/t_gen_nonconst_bad.pl
View File

@ -11,6 +11,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
lint(
v_flags => [], # To avoid -I
v_flags2 => [], # To avoid -I
verilator_flags => ["--lint-only"], # To avoid -I
verilator_flags2 => [], # To avoid -I
fails => 1,
expect_filename => $Self->{golden_filename},
);

10
test_regress/t/t_gen_nonconst_bad.v
View File

@ -1,15 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
if ($test$plusargs("BAD-non-constant")) begin
initial $stop;
end
case (1)
$test$plusargs("BAD-non-constant"): initial $stop;
endcase
nfound nfound();
endmodule

13
test_regress/t/t_lint_pragma_protected_bad.out
View File

@ -38,7 +38,16 @@
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:63:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:1: `pragma is missing a pragma_expression.
72 | `pragma
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: multiple `pragma protected encoding sections
66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: line_length must be multiple of 4 for BASE64
66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:68:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 line too long in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:77:1: `pragma is missing a pragma_expression.
77 | `pragma
| ^~~~~~~
%Error: Exiting due to

5
test_regress/t/t_lint_pragma_protected_bad.v
View File

@ -63,6 +63,11 @@ ZCBXb3JrIGFzIG==
aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVyTOOLONG
`pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
`pragma protect data_block
aW5p
`pragma protect end_protected
// Should trigger unknown pragma warning, although in principle unknown pragmas should be safely ignored.

4
test_regress/t/t_preproc_eof5_bad.out Normal file
View File

@ -0,0 +1,4 @@
%Error: t/t_preproc_eof5_bad.v:7:1: EOF in (*
7 | (* attr
| ^
%Error: Exiting due to

19
test_regress/t/t_preproc_eof5_bad.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

7
test_regress/t/t_preproc_eof5_bad.v Normal file
View File

@ -0,0 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
(* attr

2
test_regress/t/t_savable_coverage_bad.out Normal file
View File

@ -0,0 +1,2 @@
%Error: Unsupported: --coverage and --savable not supported together
%Error: Exiting due to

21
test_regress/t/t_savable_coverage_bad.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2020 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
v_flags2 => ["--savable --coverage"],
save_time => 500,
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

8
test_regress/t/t_savable_coverage_bad.v Normal file
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@ -0,0 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
endmodule

87
test_regress/t/t_select_bad_range4.out Normal file
View File

@ -0,0 +1,87 @@
%Error: t/t_select_bad_range4.v:17:8: Width of bit range is huge; vector of over 1 billion bits: 0x20000001
: ... In instance t
17 | reg [1<<29 : 0] hugerange;
| ^
%Error: t/t_select_bad_range4.v:20:16: Width of :+ or :- is < 0: 32'hffffffff
: ... In instance t
20 | sel2 = mi[44 +: -1];
| ^
%Error-UNSUPPORTED: t/t_select_bad_range4.v:20:16: Unsupported: left < right of bit extract: 2<4
: ... In instance t
20 | sel2 = mi[44 +: -1];
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Warning-WIDTH: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits.
: ... In instance t
20 | sel2 = mi[44 +: -1];
| ^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000
: ... In instance t
21 | sel2 = mi[44 +: 1<<29];
| ^
%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Extracting 20000000 bits from only 6 bit number
: ... In instance t
21 | sel2 = mi[44 +: 1<<29];
| ^
%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Selection index out of range: 20000003:4 outside 2d:28
: ... In instance t
21 | sel2 = mi[44 +: 1<<29];
| ^
%Warning-WIDTH: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits.
: ... In instance t
21 | sel2 = mi[44 +: 1<<29];
| ^
%Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst'
: ... In instance t
22 | sel2 = mi[44 +: nonconst];
| ^~~~~~~~
%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit extract isn't a constant
: ... In instance t
22 | sel2 = mi[44 +: nonconst];
| ^~~~~~~~
%Warning-WIDTH: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
: ... In instance t
22 | sel2 = mi[44 +: nonconst];
| ^
%Warning-WIDTH: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits.
: ... In instance t
23 | sel2 = mi[nonconst];
| ^~~~~~~~
%Warning-WIDTH: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
: ... In instance t
23 | sel2 = mi[nonconst];
| ^
%Error: t/t_select_bad_range4.v:24:17: Expecting expression to be constant, but variable isn't const: 'nonconst'
: ... In instance t
24 | sel2 = mi[nonconst : nonconst];
| ^~~~~~~~
%Error: t/t_select_bad_range4.v:24:28: Expecting expression to be constant, but variable isn't const: 'nonconst'
: ... In instance t
24 | sel2 = mi[nonconst : nonconst];
| ^~~~~~~~
%Error: t/t_select_bad_range4.v:24:17: First value of [a:b] isn't a constant, maybe you want +: or -:
: ... In instance t
24 | sel2 = mi[nonconst : nonconst];
| ^~~~~~~~
%Error: t/t_select_bad_range4.v:24:28: Second value of [a:b] isn't a constant, maybe you want +: or -:
: ... In instance t
24 | sel2 = mi[nonconst : nonconst];
| ^~~~~~~~
%Warning-WIDTH: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
: ... In instance t
24 | sel2 = mi[nonconst : nonconst];
| ^
%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 20000001 bits from only 6 bit number
: ... In instance t
25 | sel2 = mi[1<<29 : 0];
| ^
%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Selection index out of range: 1fffffd8:ffffffd8 outside 2d:28
: ... In instance t
25 | sel2 = mi[1<<29 : 0];
| ^
%Warning-WIDTH: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits.
: ... In instance t
25 | sel2 = mi[1<<29 : 0];
| ^
%Error: Exiting due to

19
test_regress/t/t_select_bad_range4.pl Executable file
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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

27
test_regress/t/t_select_bad_range4.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, unk, nonconst, mi
);
input clk;
input unk;
input nonconst;
input [45:40] mi;
reg [3:0] sel2;
reg [1<<29 : 0] hugerange;
always @ (posedge clk) begin
sel2 = mi[44 +: -1];
sel2 = mi[44 +: 1<<29];
sel2 = mi[44 +: nonconst];
sel2 = mi[nonconst];
sel2 = mi[nonconst : nonconst];
sel2 = mi[1<<29 : 0];
end
endmodule

19
test_regress/t/t_select_bad_range5.out Normal file
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%Error: t/t_select_bad_range5.v:16:19: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
: ... In instance t
16 | assign mi = unk[3:2];
| ^
%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Extracting 2 bits from only 1 bit number
: ... In instance t
16 | assign mi = unk[3:2];
| ^
... For warning description see https://verilator.org/warn/SELRANGE?v=latest
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Selection index out of range: 3:2 outside 1:0
: ... In instance t
16 | assign mi = unk[3:2];
| ^
%Warning-WIDTH: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits.
: ... In instance t
16 | assign mi = unk[3:2];
| ^
%Error: Exiting due to

19
test_regress/t/t_select_bad_range5.pl Executable file
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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

17
test_regress/t/t_select_bad_range5.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, unk, mi
);
input clk;
input unk;
output mi;
assign mi = unk[3:2];
endmodule

8
test_regress/t/t_sys_fscanf_bad.out Normal file
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%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:13:7: Unsupported: %l in $fscanf
13 | $fscanf(file, "%l", i);
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:14:7: Unsupported: %m in $fscanf
14 | $fscanf(file, "%m", i);
| ^~~~~~~
%Error: Exiting due to

19
test_regress/t/t_sys_fscanf_bad.pl Executable file
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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

18
test_regress/t/t_sys_fscanf_bad.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
integer file;
integer i;
initial begin
$fscanf(file, "%l", i); // Bad
$fscanf(file, "%m", i); // Bad
$write("*-* All Finished *-*\n");
$finish;
end
endmodule