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56 lines
1.0 KiB
Systemverilog
56 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class NestedCls #(
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parameter A = 0
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);
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parameter B = 0;
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endclass
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NestedCls #(1, 2) cls;
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mod1 # ( 3, 4, 5 ) i_mod1 ();
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mod2 # ( 5, 12, 13 ) i_mod2 ();
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mod3 # ( 7, 24, 25 ) i_mod3 ();
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intf1 # ( 8, 15, 17 ) i_intf1 ();
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prgm1 # ( 9, 40, 41 ) i_prgm1 ();
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endmodule
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`define CHECK_PARAMS if (A**2 + B**2 != C**2) $error("A**2 + B**2 != C**2")
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module mod1 # (
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parameter A = 1, B = 1
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);
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parameter C = 1;
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`CHECK_PARAMS;
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endmodule
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module mod2 ();
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parameter A = 1, B = 1, C = 1;
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`CHECK_PARAMS;
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endmodule
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module mod3 #() ();
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parameter A = 1, B = 1, C = 1;
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`CHECK_PARAMS;
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endmodule
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interface intf1 # (
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parameter A = 1, B = 1
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);
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parameter C = 1;
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`CHECK_PARAMS;
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endinterface
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program prgm1 # (
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parameter A = 1, B = 1
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);
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parameter C = 1;
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`CHECK_PARAMS;
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endprogram
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