mirror of
https://github.com/verilator/verilator.git
synced 2025-04-05 04:02:37 +00:00
Support converting parameters inside modules to localparams (#4511)
This commit is contained in:
Anthony Donlon
GitHub
parent
a9256d4758
commit
60e9827ffe
@ -234,6 +234,7 @@ private:
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bool m_inLibrary : 1; // From a library, no error if not used, never top level
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bool m_dead : 1; // LinkDot believes is dead; will remove in Dead visitors
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bool m_hasGParam : 1; // Has global parameter (for link)
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bool m_hasParameterList : 1; // Has #() for parameter declaration
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bool m_hierBlock : 1; // Hierarchical Block marked by HIER_BLOCK pragma
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bool m_internal : 1; // Internally created
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bool m_recursive : 1; // Recursive module
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@ -248,6 +249,7 @@ protected:
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, m_inLibrary{false}
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, m_dead{false}
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, m_hasGParam{false}
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, m_hasParameterList{false}
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, m_hierBlock{false}
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, m_internal{false}
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, m_recursive{false}
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@ -277,6 +279,8 @@ public:
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bool dead() const { return m_dead; }
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void hasGParam(bool flag) { m_hasGParam = flag; }
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bool hasGParam() const { return m_hasGParam; }
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void hasParameterList(bool flag) { m_hasParameterList = flag; }
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bool hasParameterList() const { return m_hasParameterList; }
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void hierBlock(bool flag) { m_hierBlock = flag; }
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bool hierBlock() const { return m_hierBlock; }
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void internal(bool flag) { m_internal = flag; }
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@ -1660,7 +1664,7 @@ class AstVar final : public AstNode {
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VVarAttrClocker m_attrClocker;
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MTaskIdSet m_mtaskIds; // MTaskID's that read or write this var
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int m_pinNum = 0; // For XML, if non-zero the connection pin number
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bool m_ansi : 1; // ANSI port list variable (for dedup check)
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bool m_ansi : 1; // Params or pins declared in the module header, rather than the body
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bool m_declTyped : 1; // Declared as type (for dedup check)
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bool m_tristate : 1; // Inout or triwire or trireg
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bool m_primaryIO : 1; // In/out to top level (or directly assigned from same)
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@ -66,6 +66,7 @@ private:
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AstNodeExpr* m_defaultOutSkewp = nullptr; // Current default output skew
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int m_genblkAbove = 0; // Begin block number of if/case/for above
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int m_genblkNum = 0; // Begin block number, 0=none seen
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int m_beginDepth = 0; // How many begin blocks above current node within current AstNodeModule
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VLifetime m_lifetime = VLifetime::STATIC; // Propagating lifetime
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bool m_insideLoop = false; // True if the node is inside a loop
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@ -312,7 +313,17 @@ private:
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if (nodep->lifetime().isNone() && nodep->varType() != VVarType::PORT) {
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nodep->lifetime(m_lifetime);
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}
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if (nodep->isGParam() && !nodep->isAnsi()) { // shadow some parameters into localparams
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if (m_beginDepth > 0
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|| (m_beginDepth == 0
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&& (m_modp->hasParameterList() || VN_IS(m_modp, Class)
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|| VN_IS(m_modp, Package)))) {
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nodep->varType(VVarType::LPARAM);
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}
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}
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if (nodep->isGParam() && m_modp) m_modp->hasGParam(true);
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if (nodep->isParam() && !nodep->valuep()
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&& nodep->fileline()->language() < V3LangCode::L1800_2009) {
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nodep->v3warn(NEWERSTD,
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@ -619,6 +630,7 @@ private:
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VL_RESTORER(m_modp);
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VL_RESTORER(m_genblkAbove);
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VL_RESTORER(m_genblkNum);
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VL_RESTORER(m_beginDepth);
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VL_RESTORER(m_lifetime);
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{
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// Module: Create sim table for entire module and iterate
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@ -628,6 +640,7 @@ private:
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m_modp = nodep;
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m_genblkAbove = 0;
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m_genblkNum = 0;
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m_beginDepth = 0;
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m_valueModp = nodep;
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m_lifetime = nodep->lifetime();
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if (m_lifetime.isNone()) {
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@ -658,6 +671,8 @@ private:
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void visit(AstBegin* nodep) override {
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V3Config::applyCoverageBlock(m_modp, nodep);
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cleanFileline(nodep);
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VL_RESTORER(m_beginDepth);
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m_beginDepth++;
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const AstNode* const backp = nodep->backp();
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// IEEE says directly nested item is not a new block
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// The genblk name will get attached to the if true/false LOWER begin block(s)
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@ -130,6 +130,13 @@ public:
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UASSERT_OBJ(!m_sympStack.empty(), nodep, "symbol stack underflow");
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m_symCurrentp = m_sympStack.back();
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}
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AstNodeModule* findTopNodeModule(FileLine* fl, bool requireNoneNull = true) {
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for (VSymEnt* const symp : vlstd::reverse_view(m_sympStack)) {
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if (AstNodeModule* const modp = VN_CAST(symp->nodep(), NodeModule)) return modp;
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}
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if (requireNoneNull) fl->v3fatalSrc("fail to find current module");
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return nullptr;
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}
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void showUpward() { // LCOV_EXCL_START
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UINFO(1, "ParseSym Stack:\n");
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for (VSymEnt* const symp : vlstd::reverse_view(m_sympStack)) {
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@ -719,7 +719,6 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
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adtypep = VN_AS(refp->dtypep()->skipRefp(), UnpackArrayDType);
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} else {
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AstSliceSel* const selp = VN_AS(ref.nodep(), SliceSel);
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UASSERT_OBJ(selp, ref.nodep(), "Unexpected op is registered");
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refp = VN_AS(selp->fromp(), VarRef);
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UASSERT_OBJ(refp, selp, "Unexpected op is registered");
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adtypep = VN_AS(selp->dtypep()->skipRefp(), UnpackArrayDType);
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@ -84,7 +84,6 @@ public:
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AstNodeDType* m_memDTypep = nullptr; // Pointer to data type for next member declaration
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AstDelay* m_netDelayp = nullptr; // Pointer to delay for next signal declaration
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AstStrengthSpec* m_netStrengthp = nullptr; // Pointer to strength for next net declaration
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AstNodeModule* m_modp = nullptr; // Last module for timeunits
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FileLine* m_instModuleFl = nullptr; // Fileline of module referenced for instantiations
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AstPin* m_instParamp = nullptr; // Parameters for instantiations
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string m_instModule; // Name of module referenced for instantiations
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@ -93,10 +92,9 @@ public:
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VLifetime m_varLifetime; // Static/Automatic for next signal
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bool m_impliedDecl = false; // Allow implied wire declarations
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bool m_varDeclTyped = false; // Var got reg/wire for dedup check
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bool m_pinAnsi = false; // In ANSI port list
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bool m_pinAnsi = false; // In ANSI parameter or port list
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bool m_tracingParse = true; // Tracing disable for parser
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bool m_inImplements = false; // Is inside class implements list
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bool m_insideClass = false; // Is inside a class body
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bool m_insideProperty = false; // Is inside property declaration
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bool m_typedPropertyPort = false; // Typed property port occurred on port lists
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bool m_modportImpExpActive
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@ -317,14 +315,12 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
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#define VARRESET_LIST(decl) \
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{ \
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GRAMMARP->m_pinNum = 1; \
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GRAMMARP->m_pinAnsi = false; \
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VARRESET(); \
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VARDECL(decl); \
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} // Start of pinlist
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#define VARRESET_NONLIST(decl) \
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{ \
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GRAMMARP->m_pinNum = 0; \
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GRAMMARP->m_pinAnsi = false; \
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VARRESET(); \
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VARDECL(decl); \
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} // Not in a pinlist
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@ -1209,11 +1205,14 @@ description: // ==IEEE: description
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timeunits_declaration<nodep>: // ==IEEE: timeunits_declaration
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yTIMEUNIT yaTIMENUM ';'
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{ PARSEP->timescaleMod($<fl>2, GRAMMARP->m_modp, true, $2, false, 0); $$ = nullptr; }
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{ PARSEP->timescaleMod($<fl>2, SYMP->findTopNodeModule($<fl>1, false), true, $2, false, 0);
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$$ = nullptr; }
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| yTIMEUNIT yaTIMENUM '/' yaTIMENUM ';'
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{ PARSEP->timescaleMod($<fl>2, GRAMMARP->m_modp, true, $2, true, $4); $$ = nullptr; }
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{ PARSEP->timescaleMod($<fl>2, SYMP->findTopNodeModule($<fl>1, false), true, $2, true, $4);
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$$ = nullptr; }
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| yTIMEPRECISION yaTIMENUM ';'
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{ PARSEP->timescaleMod($<fl>2, GRAMMARP->m_modp, false, 0, true, $2); $$ = nullptr; }
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{ PARSEP->timescaleMod($<fl>2, SYMP->findTopNodeModule($<fl>1, false), false, 0, true, $2);
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$$ = nullptr; }
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;
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//**********************************************************************
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@ -1223,7 +1222,6 @@ package_declaration: // ==IEEE: package_declaration
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packageFront package_itemListE yENDPACKAGE endLabelE
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{ $1->modTrace(GRAMMARP->allTracingOn($1->fileline())); // Stash for implicit wires, etc
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if ($2) $1->addStmtsp($2);
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>4, $1, $4); }
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;
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@ -1243,8 +1241,7 @@ packageFront<nodeModulep>:
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$$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
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$$->timeunit(PARSEP->timeLastUnit());
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PARSEP->rootp()->addModulesp($$);
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SYMP->pushNew($$);
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GRAMMARP->m_modp = $$; }
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SYMP->pushNew($$); }
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;
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package_itemListE<nodep>: // IEEE: [{ package_item }]
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@ -1343,7 +1340,6 @@ module_declaration: // ==IEEE: module_declaration
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if ($2) $1->addStmtsp($2);
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if ($3) $1->addStmtsp($3);
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if ($5) $1->addStmtsp($5);
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>7, $1, $7); }
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| udpFront portsStarE ';'
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@ -1352,7 +1348,6 @@ module_declaration: // ==IEEE: module_declaration
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if ($2) $1->addStmtsp($2);
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if ($4) $1->addStmtsp($4);
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GRAMMARP->m_tracingParse = true;
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>6, $1, $6); }
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//
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@ -1371,8 +1366,7 @@ modFront<nodeModulep>:
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$$->timeunit(PARSEP->timeLastUnit());
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$$->unconnectedDrive(PARSEP->unconnectedDrive());
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PARSEP->rootp()->addModulesp($$);
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SYMP->pushNew($$);
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GRAMMARP->m_modp = $$; }
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SYMP->pushNew($$); }
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| modFront sigAttrScope { $$ = $1; }
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;
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@ -1419,13 +1413,18 @@ parameter_value_assignmentClass<pinp>: // IEEE: [ parameter_value_assignment ]
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parameter_port_listE<nodep>: // IEEE: parameter_port_list + empty == parameter_value_assignment
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/* empty */ { $$ = nullptr; }
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| '#' '(' ')' { $$ = nullptr; }
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| '#' '(' ')' { $$ = nullptr;
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SYMP->findTopNodeModule($<fl>1)->hasParameterList(true); }
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// // IEEE: '#' '(' list_of_param_assignments { ',' parameter_port_declaration } ')'
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// // IEEE: '#' '(' parameter_port_declaration { ',' parameter_port_declaration } ')'
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// // Can't just do that as "," conflicts with between vars and between stmts, so
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// // split into pre-comma and post-comma parts
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| '#' '(' {VARRESET_LIST(GPARAM);} paramPortDeclOrArgList ')'
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{ $$ = $4; VARRESET_NONLIST(UNKNOWN); }
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| '#' '(' { VARRESET_LIST(GPARAM);
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SYMP->findTopNodeModule($<fl>1)->hasParameterList(true);
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GRAMMARP->m_pinAnsi = true; }
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/*cont*/ paramPortDeclOrArgList ')' { $$ = $4;
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VARRESET_NONLIST(UNKNOWN);
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GRAMMARP->m_pinAnsi = false; }
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// // Note legal to start with "a=b" with no parameter statement
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;
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@ -1451,7 +1450,10 @@ portsStarE<nodep>: // IEEE: .* + list_of_ports + list_of_port_decla
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| '(' ')' { $$ = nullptr; }
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// // .* expanded from module_declaration
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//UNSUP '(' yP_DOTSTAR ')' { UNSUP }
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| '(' {VARRESET_LIST(PORT);} list_of_ports ')' { $$ = $3; VARRESET_NONLIST(UNKNOWN); }
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| '(' { VARRESET_LIST(PORT);
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GRAMMARP->m_pinAnsi = true; }
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/*cont*/ list_of_ports ')' { $$ = $3; VARRESET_NONLIST(UNKNOWN);
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GRAMMARP->m_pinAnsi = false; }
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;
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list_of_portsE<nodep>: // IEEE: list_of_ports + list_of_port_declarations
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@ -1596,7 +1598,7 @@ portDirNetE: // IEEE: part of port, optional net type and/or
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// // The higher level rule may override this VARDTYPE with one later in the parse.
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| port_direction { VARDECL(PORT); VARDTYPE_NDECL(nullptr); }
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| port_direction { VARDECL(PORT); } net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL
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| net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL
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| net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL
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;
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port_declNetE: // IEEE: part of port_declaration, optional net type
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@ -1706,7 +1708,6 @@ program_declaration: // IEEE: program_declaration + program_nonansi_h
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if ($2) $1->addStmtsp($2);
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if ($3) $1->addStmtsp($3);
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if ($5) $1->addStmtsp($5);
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>7, $1, $7); }
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| yEXTERN pgmFront parameter_port_listE portsStarE ';'
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@ -1722,8 +1723,7 @@ pgmFront<nodeModulep>:
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$$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
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$$->timeunit(PARSEP->timeLastUnit());
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PARSEP->rootp()->addModulesp($$);
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SYMP->pushNew($$);
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GRAMMARP->m_modp = $$; }
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SYMP->pushNew($$); }
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;
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program_itemListE<nodep>: // ==IEEE: [{ program_item }]
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@ -1958,23 +1958,19 @@ net_type: // ==IEEE: net_type
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;
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varParamReset:
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yPARAMETER
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{ if (GRAMMARP->m_insideClass) {
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VARRESET_NONLIST(LPARAM);
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} else {
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VARRESET_NONLIST(GPARAM);
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} }
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yPARAMETER { VARRESET_NONLIST(GPARAM); }
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| yLOCALPARAM { VARRESET_NONLIST(LPARAM); }
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// Note that the type of these params could be modified later according to context (see V3LinkParse)
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;
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port_direction: // ==IEEE: port_direction + tf_port_direction
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// // IEEE 19.8 just "input" FIRST forces type to wire - we'll ignore that here
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// // Only used for ANSI declarations
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yINPUT { GRAMMARP->m_pinAnsi = true; VARIO(INPUT); }
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| yOUTPUT { GRAMMARP->m_pinAnsi = true; VARIO(OUTPUT); }
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| yINOUT { GRAMMARP->m_pinAnsi = true; VARIO(INOUT); }
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| yREF { GRAMMARP->m_pinAnsi = true; VARIO(REF); }
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| yCONST__REF yREF { GRAMMARP->m_pinAnsi = true; VARIO(CONSTREF); }
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yINPUT { VARIO(INPUT); }
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| yOUTPUT { VARIO(OUTPUT); }
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| yINOUT { VARIO(INOUT); }
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| yREF { VARIO(REF); }
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| yCONST__REF yREF { VARIO(CONSTREF); }
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;
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port_directionReset: // IEEE: port_direction that starts a port_declaraiton
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@ -5960,12 +5956,12 @@ property_port_itemAssignment<nodep>: // IEEE: part of property_port_item/sequen
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property_port_itemDirE:
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/* empty */
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{ GRAMMARP->m_pinAnsi = true; VARIO(INPUT); }
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{ VARIO(INPUT); }
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| yLOCAL__ETC
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{ GRAMMARP->m_pinAnsi = true; VARIO(INPUT);
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{ VARIO(INPUT);
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BBUNSUP($1, "Unsupported: property port 'local'"); }
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| yLOCAL__ETC yINPUT
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{ GRAMMARP->m_pinAnsi = true; VARIO(INPUT);
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{ VARIO(INPUT);
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BBUNSUP($1, "Unsupported: property port 'local'"); }
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;
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@ -6743,7 +6739,6 @@ checker_declaration<nodep>: // ==IEEE: part of checker_declaration
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$1->modTrace(GRAMMARP->allTracingOn($1->fileline()));
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if ($2) $1->addStmtsp($2);
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if ($4) $1->addStmtsp($4);
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>6, $1, $6); }
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;
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@ -6756,8 +6751,7 @@ checkerFront<nodeModulep>: // IEEE: part of checker_declaration
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$$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
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$$->timeunit(PARSEP->timeLastUnit());
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$$->unconnectedDrive(PARSEP->unconnectedDrive());
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SYMP->pushNew($$);
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GRAMMARP->m_modp = $$; }
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SYMP->pushNew($$); }
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;
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checker_port_listE<nodep>: // IEEE: [ ( [ checker_port_list ] ) ]
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@ -6833,7 +6827,6 @@ class_declaration<nodep>: // ==IEEE: part of class_declaration
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classFront parameter_port_listE classExtendsE classImplementsE ';'
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/*mid*/ { // Allow resolving types declared in base extends class
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if ($<scp>3) SYMP->importExtends($<scp>3);
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GRAMMARP->m_insideClass = true;
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}
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/*cont*/ class_itemListE yENDCLASS endLabelE
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{ $$ = $1; $1->addMembersp($2);
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@ -6842,7 +6835,6 @@ class_declaration<nodep>: // ==IEEE: part of class_declaration
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$1->addExtendsp($4);
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$1->addMembersp($7);
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SYMP->popScope($$);
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GRAMMARP->m_insideClass = false;
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GRAMMARP->endLabel($<fl>9, $1, $9); }
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;
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23
test_regress/t/t_param_implicit_local_bad.out
Normal file
23
test_regress/t/t_param_implicit_local_bad.out
Normal file
@ -0,0 +1,23 @@
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%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:15:20: Parameter pin not found: '__paramNumber2'
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15 | NestedCls #(1, 2) cls;
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| ^
|
||||
... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:17:21: Parameter pin not found: '__paramNumber3'
|
||||
17 | mod1 # ( 3, 4, 5 ) i_mod1 ();
|
||||
| ^
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:15: Parameter pin not found: '__paramNumber1'
|
||||
19 | mod3 # ( 7, 24, 25 ) i_mod3 ();
|
||||
| ^
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:18: Parameter pin not found: '__paramNumber2'
|
||||
19 | mod3 # ( 7, 24, 25 ) i_mod3 ();
|
||||
| ^~
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:22: Parameter pin not found: '__paramNumber3'
|
||||
19 | mod3 # ( 7, 24, 25 ) i_mod3 ();
|
||||
| ^~
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:20:22: Parameter pin not found: '__paramNumber3'
|
||||
20 | intf1 # ( 8, 15, 17 ) i_intf1 ();
|
||||
| ^~
|
||||
%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:21:22: Parameter pin not found: '__paramNumber3'
|
||||
21 | prgm1 # ( 9, 40, 41 ) i_prgm1 ();
|
||||
| ^~
|
||||
%Error: Exiting due to
|
||||
19
test_regress/t/t_param_implicit_local_bad.pl
Executable file
19
test_regress/t/t_param_implicit_local_bad.pl
Executable file
@ -0,0 +1,19 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(linter => 1);
|
||||
|
||||
lint(
|
||||
fails => 1,
|
||||
expect_filename => $Self->{golden_filename},
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
55
test_regress/t/t_param_implicit_local_bad.v
Normal file
55
test_regress/t/t_param_implicit_local_bad.v
Normal file
@ -0,0 +1,55 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2023 by Anthony Donlon.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
|
||||
module t;
|
||||
class NestedCls #(
|
||||
parameter A = 0
|
||||
);
|
||||
parameter B = 0;
|
||||
endclass
|
||||
|
||||
NestedCls #(1, 2) cls;
|
||||
|
||||
mod1 # ( 3, 4, 5 ) i_mod1 ();
|
||||
mod2 # ( 5, 12, 13 ) i_mod2 ();
|
||||
mod3 # ( 7, 24, 25 ) i_mod3 ();
|
||||
intf1 # ( 8, 15, 17 ) i_intf1 ();
|
||||
prgm1 # ( 9, 40, 41 ) i_prgm1 ();
|
||||
endmodule
|
||||
|
||||
`define CHECK_PARAMS if (A**2 + B**2 != C**2) $error("A**2 + B**2 != C**2")
|
||||
|
||||
module mod1 # (
|
||||
parameter A = 1, B = 1
|
||||
);
|
||||
parameter C = 1;
|
||||
`CHECK_PARAMS;
|
||||
endmodule
|
||||
|
||||
module mod2 ();
|
||||
parameter A = 1, B = 1, C = 1;
|
||||
`CHECK_PARAMS;
|
||||
endmodule
|
||||
|
||||
module mod3 #() ();
|
||||
parameter A = 1, B = 1, C = 1;
|
||||
`CHECK_PARAMS;
|
||||
endmodule
|
||||
|
||||
interface intf1 # (
|
||||
parameter A = 1, B = 1
|
||||
);
|
||||
parameter C = 1;
|
||||
`CHECK_PARAMS;
|
||||
endinterface
|
||||
|
||||
program prgm1 # (
|
||||
parameter A = 1, B = 1
|
||||
);
|
||||
parameter C = 1;
|
||||
`CHECK_PARAMS;
|
||||
endprogram
|
||||
@ -11,10 +11,7 @@ module t (/*AUTOARG*/
|
||||
parameter PAR = 3;
|
||||
input clk;
|
||||
|
||||
`ifdef verilator
|
||||
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
|
||||
defparam m3.FROMDEFP = 19;
|
||||
`endif
|
||||
|
||||
m3 #(.P3(PAR),
|
||||
.P2(2))
|
||||
@ -36,7 +33,8 @@ module m3
|
||||
parameter UNCH = 99,
|
||||
parameter P1 = 10,
|
||||
parameter P2 = 20,
|
||||
P3 = 30
|
||||
P3 = 30,
|
||||
parameter FROMDEFP = 11
|
||||
)
|
||||
(/*AUTOARG*/
|
||||
// Inputs
|
||||
@ -45,8 +43,6 @@ module m3
|
||||
input clk;
|
||||
localparam LOC = 13;
|
||||
|
||||
parameter FROMDEFP = 11;
|
||||
|
||||
initial begin
|
||||
$display("%x %x %x",P1,P2,P3);
|
||||
end
|
||||
@ -55,8 +51,6 @@ module m3
|
||||
if (P1 !== 10) $stop;
|
||||
if (P2 !== 2) $stop;
|
||||
if (P3 !== 3) $stop;
|
||||
`ifdef verilator
|
||||
if (FROMDEFP !== 19) $stop;
|
||||
`endif
|
||||
end
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user