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34 lines
742 B
Systemverilog
34 lines
742 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module sub(input wire clk, cpu_reset);
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reg reset_r;
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always @(posedge clk) begin
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reset_r <= cpu_reset; // The problematic one
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end
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endmodule
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module TOP(/*AUTOARG*/
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// Inputs
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clk, reset_l
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);
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input clk;
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input reset_l;
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reg sync_0, sync_1, sync_2;
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wire _cpu_reset_chain_io_q = sync_0;
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sub sub (.clk(clk),
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.cpu_reset(_cpu_reset_chain_io_q | !reset_l));
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always @(posedge clk) begin
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sync_0 <= sync_1;
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sync_1 <= sync_2;
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sync_2 <= !reset_l;
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end
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endmodule
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