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81 lines
1.0 KiB
Systemverilog
81 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Udi Finkelstein.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off MULTITOP */
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// First, test we haven't broken normal ports
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module t1();
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endmodule
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module t2;
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endmodule
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module t3(a);
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input a;
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endmodule
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module t4(a, b);
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input a, b;
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endmodule
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module t5(a,);
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input a;
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endmodule
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module t6(a,,);
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input a;
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endmodule
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module t7(a,b,);
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input a, b;
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endmodule
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module t8(a,b,,);
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input a, b;
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endmodule
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module t9(a,,b);
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input a, b;
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endmodule
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module t10(a,,b,);
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input a, b;
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endmodule
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module t11(a,,b,,);
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input a, b;
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endmodule
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module t12(,a,,b);
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input a, b;
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endmodule
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module t13(,a,,b,);
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input a, b;
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endmodule
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module t14(,a,,b,,);
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input a, b;
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endmodule
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module t15(,,a,,b);
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input a, b;
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endmodule
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module t16(,,a,,b,);
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input a, b;
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endmodule
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module t17(,,a,,b,,);
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input a, b;
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endmodule
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module t18(,);
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endmodule
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/* verilator lint_off NULLPORT */
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module t19(,,);
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endmodule
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